EDN Access--01.01.98 Capacitor model accounts for temperature, bias

-January 01, 1998

January 1, 1998

Capacitor model accounts for temperature, bias

Debra Horvitz, Galahad Systems, Laguna Hills, CA

The basic passive components in Spice are all ideal elements that include no parasitics, such as capacitor ESR and inductor series resistance. Although it is common to represent a real capacitor with a combination of ESR, equivalent series inductance (ESL), and nominal capacitance (C), a more realistic subcircuit representation of a ceramic capacitor takes many more capacitor characteristics into account (Figure 1a).

This model features an ESR value, RESR, that depends on frequency, dc bias, and temperature. The capacitance, CNOM, depends on dc bias and temperature. The parallel resistor, RP, which represents the leakage or insulation resistance, is also temperature-dependent. RCP and CP create a secondary and parallel resonance that represents a capacitance that shunts the RLC elements. CP depends on the body and chip size. LX keeps the parallel resonance in check and accounts for pad and lead inductances.

The netlist of the .SUBCKT model (Figure 1b) incorporates a number of equations for various capacitor characteristics (Figure 1c). For example, the definition of RESR in Figure 1b includes Rnom, which is the minimum resistance at the self-resonance frequency. The "Fres" variable determines this frequency. The 1.5 factor in the frequency term widens the self resonance; that is, produces a wider frequency response around the resonance frequency. A value of 1.5 produces the best fit to actual data.

The model incorporates frequency dependence by including the "Freq" term in the resistance expression. During an ac analysis, Spice sets the Freq term to the simulation frequency. During a transient analysis, Freq is equal to 0, which makes the ESR large. The "R=" part is necessary only when Spice re-evaluates the resistance during the simulation. Spice automatically evaluates the expressions and variables in braces, {}, before running the simulation.

Note that in IsSpice4 (Intusoft, San Pedro, CA), the version of Spice this model uses, you can also use a ratio of Laplace polynomial expressions. These Laplace blocks have both an ac and a transient response and are useful for deriving virtually any linear transfer function of s.

TTest is the temperature of the capacitor, which you can set using the keyword TEMP (using a "= .Options Temp value" statement) in the main Spice netlist. Vbias is the dc bias of the capacitor. Vnom is the voltage at which the capacitance drops by 20%.

Figure 2a and the corresponding netlist (Figure 2b) show the simulation of a 0.22-µF ceramic capacitor (X7R 1206) with a Fres variable of 6.38 MHz and a Vnom of 30. Reference 1 provides further derivation of and reasoning behind the equations in Figure 2. It also provides equations for NP0, C0G, and Y5V capacitor families. To download the file, click here: DI-SIG, #2119. (DI #2119)

  1. Prymak, John, "Spice modeling of capacitors," CARTS 95: 15th Capacitor and Resistor Technology Symposium, March 1995.

Figure 1

(a)   01d2119a
(b)  1D21191B
ESR/CAP DC-BIAS VARIATION: nom*(1-(Vtest/Vnom)*0.2)
ESR(Rnom) FREQUENCY VARIATION: Rnom*(1+10*(|log(Fres/Freq)|-1.5))
ESR TEMPERATURE VARIATION: Rnom*5*((25-Ttest)/100)
C TEMPERATURE VARIATION: Cnom*(1-((Ttest-30)/85)**2*0.12)
A complete Spice capacitor model (a) includes elements that depends on frequency, dc bias, and temperature. The corresponding .SUBCKT listing (b) incorporates various equations (c) that govern the model's operation. 
Figure 2
(a)  2421192a (b)  1D21192B
The simulation of a 0.22-mF ceramic capacitor shows the impedance variation with frequency (a). In the corresponding .SUBCKT listing (b), the Fres variable is 6.38 MHz and Vnom is 30.

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