EDN Access— 10.12.95 Group-delay equalizer has gain >

-October 12, 1995

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Design Ideas:October 12, 1995

Group-delay equalizer has gain >1

Mark Weigel,
Scottsdale, AZ

For numerous applications, flat group delay (linear phase) is necessary to maintain system performance. The common group-delay equalizer of Fig 1a has unity gain and is a popular way to equalize data filters or alias filters when phase compensation is necessary. The alternative equalizer of Fig 1b, however, can provide a gain greater than one for systems that require additional gain (and when providing that gain elsewhere is impossible or impractical).

The transfer function of Fig 1a's configuration is H(s)=2F(s)-1. Notice that you can multiply H(s) by a gain factor, G, without changing the response of the transfer function so that

H(s) = G(2F(s-1).

If F(s) is a high-pass RC network with F(s)=sRC/(sRC+1), then

which provides a conjugate zero in the right-hand side of the s-plane useful for a first-order delay equalizer. You can realize a higher-order equalizer using a higher-order F(s).

The key to the operation of Fig 1b's equalizer is the way the input signal splits into two paths. Part of the signal passes through F(s) and has positive gain, and the other path exposes the original signal to negative gain. To obtain an all-pass filter characteristic, like that of eq 2, with a conjugate zero in the right half of the s-plane, the negative gain must be one-half of the positive gain, as eq 1 indicates. Thus, making a few modifications to Fig 1a yields the configuration in Fig 1b. This configuration permits a net gain greater than 1 from VIN to VOUT while restricting the negative gain to one-half the positive gain. The design equations are as follows:

As an example, assume a gain of five (G=5) is necessary. Start by selecting R1=301 Ohms, and calculate R2=452 Ohms. Select a convenient value for R3 (150 ohms), and find R4 (1653 Ohms). Setting R3 equal to R1 is another good starting point.

One benefit of this approach is that changing G does not alter the frequency response, at least to a first approximation. So, the components making up F(s) are the same in both Fig 1a and 1b. This situation is not the case with many active filter topologies for which changing the gain alters the frequency response of the circuit. As G increases in Fig 1b, the precision of the positive and negative gain becomes more important due to the differencing of the signal through the amplifier. So, designing configurations with moderate gains is easier than designing those with high gains. Note that you can easily compensate for losses in F(s) using this same technique. (DI #1767)

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