EDN Access 07.20.95 Unlocked PLL retains locked frequenc

-July 20, 1995

EDN logo

Design IdeasJuly 20, 1995

Unlocked PLL retains locked frequency

Karol Freed,
HAC, Carlsbad, CA

Using the PC2 in-phase comparator output, the circuit in Fig 1 keeps the unlocked, or free-run, frequency of a 74HC4046 PLL near the locked frequency. With no signal input, the VCO output normally adjusts to its lowest frequency (one-half the locked frequency, f0). In some applications, such a large frequency excursion may be undesirable. With the addition of D1, R3, C2, R4, and the 74HC04 inverting buffer, the free-run frequency remains near the locked frequency in the absence of a signal input.

During normal locked operation, the nominal VCO voltage at Node A is 2.25V. The PCP output is high, except during sampling time, in which a 300-nsec logic-zero glitch appears. The R4-C2 network filters out the glitch, leaving a sustained low output from the 74HC04 inverter. When the signal input is logic low (removed), the PCP and PC2 outputs are low, thus, grounding R2. The inverter's output is at 5V at this time. The voltage divider comprising R3, D1, R1, and R2 returns the voltage at Node A to the nominal 2.25V.

Diode D1 decouples the 74HC04 output from Node A, allowing the PLL to operate normally in the locked mode. You can use an ordinary silicon diode instead of the 1N5711 Schottky device. However, you use this device at the expense of a higher forward drop and increased temperature sensitivity. Reverse leakage in D[sub{1}] has negligible effects on the circuit, unless the VCO's filter-resistor values are very high. (DI #1733)


A few discrete components and an inverter make the unlocked frequency of this PLL remain near the locked frequency.

| EDN Access | feedback | subscribe to EDN! |
| design features | design ideas | columnist |

Copyright c 1995 EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.

Loading comments...

Write a Comment

To comment please Log In