EDN -- 11.09.95 carry-save addition saves logic and tim

-November 09, 1995

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Design Ideas:November 9, 1995

Carry-save addition saves logic and time

Chris Jones,
Cypress Semiconductor
San Jose, CA

Summing multiple operands is a common operation in signal-processing applications. One such application requires summing eight 16-bit operands to generate a 19-bit result. To achieve the required setup time (tS) and clock-to-output time (tCO) in the system, you need pipelining. Figure 1 shows the straightforward way to implement this multiple-operand addition with pipelining. The design, which requires 104 registers, includes two levels of pipelining registers. The external fMAX performance for this design is a function of the sum of tS based on a 16-bit addition and tCO based on an 18-bit addition, both of which take four cascaded logic cells in a Cypress pASIC380 field-programmable gate array.

Designers often use the carry-save-addition (CSA) technique for summing the partial products associated with multiplication. Figure 2, which shows the first level of the CSAs, shows how you can apply CSA to this multiple-operand adder design. In Figure 2a, in which each box represents a full-adder cell, the input operands are assigned to 32 full-adder cells. Figure 2b shows the outputs that result from this first CSA level.

Input bits A0, B0, and C0 are supplied to a full adder, whose sum and carry outputs are J0 and K1. Similarly, L0 and M1 are the sum and carry bits for the addition of D0, E0, and F0. All the other boxes represent inputs fed into full adders. The outputs of the first CSA level become inputs to a second CSA level, whose outputs go to a third CSA level, and so on.

By using CSA for this multiple operand, after four CSA levels, the eight-operand adder reduces to 2 bits of the desired result and two 16-bit operands that remain to be added (Figure 3). The advantage of this implementation over the one in Figure 1 is that the one in Figure 3 needs only one pipeline-register level instead of two. Also, the function needs only 34 registers, as opposed to the 104 Figure 1’s structure needs. The number of required logic cells thus vastly decreases. The external performance is the same in both versions, because tS is based on four CSA levels and tCO is based on a 16-bit addition. (DI #1786)

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