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EDN Access -- 02.16.95 Graphics controller handles interleaved memor

-February 16, 1995

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Design Ideas:February 16, 1995

Graphics controller handles interleaved memory


YS Tam,
Canadian Marconi Co, Kanata, ON, Canada

The Intel 82786 graphics controller does not generate a proper data-transfer cycle if your video RAM (VRAM) is organized into two interleaved banks (Fig 1). The circuit in Fig 2 overcomes this device's deficiency.

A video controller's data-transfer cycle must load the VRAM's shift register from the selected address during the video-blanking period. During normal read or write cycles, IC3's _Q output in Fig 2, is at a logic high. This state allows _CAS0 and _CAS1 to pass through without any changes. During data-transfer cycles, IC3's pin 6 goes low after the falling edge of _CAS0. This change extends the duration of _CAS0 and _CAS1 until the end of the cycle.



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