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EDN Access— 01.19.95 Backup clock controller checks time settin

-January 05, 1995

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Design Ideas:January 5, 1995

Backup clock controller checks time setting


David W Jordan,
RL Drake Co, Franklin, OH

The simple, inexpensive circuit in Fig 1 provides backup power to a clock IC during outages. The circuit also determines whether the outage caused any loss in the time setting. C1provides the backup power, and the µC's ADC reads the time after the outage.

The µC pin P1must be bidirectional, and the µC must configure this pin as an input on reset. The µC configures the pin as an output and holds its level high under normal operation. The output supplies power to the clock chip. P1must supply current to charge the clock chip and C1, which quickly charges to provide the backup power. R1limits the current from P1to a level acceptable to the output pin driver.

When power fails, D1 prevents the discharge of C1through P1. R2 reduces the power loss through the ADC input of the µC. R2 must be as large as possible without being on the order of the ADC's input impedance. This arrangement supports the TC8521A clock IC with a standard 1000-µF electrolytic capacitor for over 20 minutes.

The bidirectional P1becomes an input and prevents C1's charging when power returns. The µC can now sample the backup supply voltage through the ADC's input and determine whether the clock survived the power outage. Then, the µC can reconfigure P1as an output and set it high to recharge the capacitor. R1also serves to prevent any sharp edges on P1from glitching the clock's power supply. Note: The clock chip remains active when main power fails. So, you must disable the read, write, and chip-select signals. If you tie the chip-select pin, pin 2, to the RESET line on the TC8512A, the chip-select line goes low as power falls and returns. This connection prevents power-draining, read/write activity during the power outage. (DI #1644)


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