EDN Access -- 07.21.94 Simple timer exploits op-amp bias curren
Design Ideas:July 21, 1994
Simple timer exploits op-amp bias current
The simple, low-cost analog timer in Fig 1 exploits the parasitic input-bias current of op-amp IC1. The timer achieves long time delays even though it uses only low-value, inexpensive ceramic chip capacitors. After all, because the input-bias current is the minimum current flow into an op amp, this method produces the longest time delays possible from a given capacitor and op amp.
In operation, the op amp's inverting input draws an input-bias current, IB, from resistive divider R1/R2/R3. The voltage at the R2-R3 junction is VREF. A current approximately equal to IB also charges capacitor C1, producing a linear voltage ramp.
Assuming that C1 is initially discharged (by pushing SW1), the delay time that IC1, functioning as a comparator, takes to change state equals VREFxC1/IB. And, as a first approximation, this time constant is independent of IB. While IC1's output is low, it briefly lights the lamp L1 via Q1, SCR1, and associated components.
This circuit configuration takes care of newer op amps whose input-bias current is less than 1 nA. Otherwise, for older, high-input-bias-current op amps, just wire the inverting input of the op amp to ground directly through a resistor. The resulting circuit's time constant would be that resistor's value multiplied by C1's. However, for today's low-input-bias-current op amps, the value of this grounding resistor would have to be exceedingly high to produce usable time constants. (DI #1565)EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.