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EDN Access -- 12.22.94 Pseudonoise generator doubles its spee

-December 22, 1994

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Design Ideas:December 22, 1994

Pseudonoise generator doubles its speed


R N Mutagi,
Space Applications Centre, Ahmedabad, India

You can double the speed of a standard pseudonoise (PN) generator by using additional exclusive-OR gates and a fast 2:1 multiplexer. A PN generator built with an n-stage feedback shift register gives a maximal-length sequence of 2N-1 bits. The upper limit of the PN-generator clock depends on the device logic family. For example, a PN generator built with 74LS74 flip-flops and a 74LS86 exclusive-OR gate has a top speed of 16 to 18 MHz. Fig 1's circuit doubles this speed by implementing a phase difference of half the sequence length. The multiplexer then combines and outputs this phase difference at double the rate of the original circuit.

Fig 1a shows a seven-stage PN generator built with flip-flops and one exclusive-OR gate. The outputs of FF6 and FF7 are modulo-2. The exclusive-OR gate adds and feeds back the outputs to FF1 to obtain a maximal-length sequence. Fig 1b shows the reconfigured generator that produces two sequences at the outputs of FF6 and FF7 with a 64-bit difference between them. The multiplexer can combine these sequences to produce a 32-MHz output because the sequences can be as fast as 16 MHz. The general procedure for the connection, for any register length N with taps specified by its characteristic equation, is as follows:
  1. Cascade odd and even flip-flops separately. This circuit cascades FF1, FF3, FF5, and FF7 and FF2, FF4, and FF6 separately.

  2. Apply the exclusive-OR sum of the original taps to D2 instead of D1. In Fig 1b, XOR1 adds Q6 and Q7 and applies the result to D2.

  3. Use a second exclusive-OR gate to add the taps from one stage ahead of the original circuit. XOR2 adds Q5 and Q6 and applies the result to D1.

  4. Multiplex outputs QN and QN-1, which are Q6 and Q7 in this example. (DI #1640)


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