Advertisement
Advertisement

EDN Access — 04.28.94 2-channel ADC tags its own outpu

-April 28, 1994

EDN logo
Design Ideas:April 28, 1994

2-channel ADC tags its own output


Fred Hamilton,
National Semiconductor, Santa Clara, CA

Transferring converted data from high-speed DACs directly to system RAM to avoid µP bottlenecks is common. But, if the ADC serves more than one input, the µP obviously won't be able to select channels during the DMA period.

The circuit in Fig 1 shows a simple way to operate a 1-MHz, 12-bit ADC (IC1) in DMA mode while alternating between its two analog-input channels. The converter operates continuously, driven by the 1-MHz clock on the S/H input.

Tying RD and CS low ensures that data are always present on the ADC's output bus. The outputs of the 74HC74 flip-flop, IC2, change state on the rising edge of the end-of-conversion (EOC) signal. The flip-flop's Q drives the ADC multiplexer's address line (pin 16), and the flip-flop's Q output provides an output bit indicating the current channel. The memory stores this bit along with the 12-bit conversion value.

Because the address changes on the rising edge of the EOC signal, the change occurs well within the ADC multiplexer's setup-and-hold limits. The two 74HC541s isolate the ADC from the system's data bus.

Posted as EDN BBS /DI_SIG #1412 on the EDN readers' bulletin-board system is a compressed ZIPfile containing a detailed design writeup and a PLD program for burning the circuit into a PAL16HD8. (DI #1412)


| EDN Access | feedback | subscribe to EDN! |
| design features | design ideas |

Copyright c 0895 EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.

Loading comments...

Write a Comment

To comment please Log In

FEATURED RESOURCES