EDN Access -- 05.26.94 Security circuit eschews sophisticatio
Design Ideas:May 26, 1994
Security circuit eschews sophistication
Because of the many states involved in implementing sequential combination locks, most designers use a microcontroller or a PLD. But for those die-hard discrete designers who don't want to bother with debugging programs, here's a dead-simple circuit that verifies a security code's entry from a 10-digit keypad.
AEG, Ajax, ON, Canada
The circuit in Fig 1 verifies an 8-digit code. You preset each digit in the code sequence by installing a shunt in the respective shunt-header position. That is, to set the first digit in the code to 3, install a shunt in position 3 of SH1; to set the second digit to 7, install a shunt in position 7 of SH2, and so on.
When the circuit resets, flip-flop IC2A's output goes high, energizing the shunted output on header SH1. If a user presses the correct key on the keypad (matching the shunted position on SH1), the input voltage to IC1B and IC1C is high enough to cause a pulse on both their outputs. If the user presses the wrong key, the R1 / R2 voltage divider on the selected line supplies just enough voltage to produce a pulse only on IC1C's output.
The output of each op amp, IC1B and IC1C, clocks its own corresponding shift register, IC4 and IC3. IC3 always advances when the user presses a correct or an incorrect key. However, IC4 advances only if the user presses the correct key.
When IC3 advances, its outputs energize the next shunt header (SH2, SH3, and so on) sequentially. Only when the user (or an intruder) presses the correct key on every stroke does IC4 advance at the same rate as IC3. When the user correctly enters all the digits in the code, the last output of IC4 toggles the output-control flip-flop. If any one of the digits is wrong,
IC4's output does not advance far enough before IC3's output resets IC4.
D1 through D8 provide isolation between the shunt headers, so that only the energized shunt header has high output on its shunted line.
C1 debounces the keypad and introduces a small time delay between the output pulses of IC1C and IC1B. This delay is critical because the output of IC1B must clock IC4 to produce an output upon the last correct digit before IC3's output resets IC4.
Resistor array R3 is optional; it provides added security, so that if an intruder tries to press more than one key at a time on the keypad to bamboozle the circuit, the voltage drop across R3 is sufficient not to trigger IC1B because of the added load.
You can expand this circuit to as many keys and to as long a code sequence as you want by cascading multiple IC3s and IC4s. IC2A's output can drive an LED indicator to signal if the keypad is waiting for input or is in the middle of a code sequence. The ZIPfile attached to EDN BBS/DI_SIG #1429 contains a writeup of this design and its schematic in OrCAD format. (DI #1429)EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.