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Self-timed logic technique cuts noise and power

-June 10, 1999

Tired of struggling with the problems of global clock timing and distribution in ASIC design? A solution to at least part of that problem may lie in a change of strategy to self-timed design. A first tool for support of self-timed design is now available from Cogency Technology (Figure); the company is based in Canada, but its technology draws on work done at Manchester University, notably on the self-timed implementations of the Amulet ARM (www.cs.man.ac.uk/amulet/amulet1_up.html) architecture. Self-timed design uses many techniques previously labelled "asynchronous" and therefore undesirable in current EDA design flows but with additional structure to support that style. Self-timed design propagates signals by a request/acknowledge handshake from each level of logic to the next-in this case, by a four-phase micropipeline. The mantra is "think global; clock local," meaning that each functional block is a separate timing regime. The benefits of this approach are that all logic executes in minimal time, which is often faster than a clocked structure. The approach saves power because, without data flow, no circuit activity occurs. The technique also reduces noise because no global clocking with multiples and submultiples takes place. ST-V self-timed Verilog and the ChannelSim self-timed verification environment provide support for designing this circuitry. You can also use and interact with conventional tools for logic areas that do not benefit from the self-timed designs, such as many datapath structures. Self-timed circuit synthesis will be the next target for a focussed tool; target markets are applications such as mobile-handset design, in which power and noise are key considerations.

Cogency Europe, Slough, UK. +44 1753 708723, www.cogency.com.

-by Graham Prophet

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