Get ready for M-PCIe testing

-October 25, 2013

The PCI-SIG, the organization responsible for PCI Express, and the MIPI Alliance, the organization behind M-PHY, are in the process of finalizing a new M-PCIe specification that combines the low-power, flexible signaling electrical performance of M-PHY with the interoperability and I/O functionality of PCIe.  For designers who in many case are still coming up to speed on the latest PCIe 3.0 and M-PHY technologies, this new M-PCIe technology will present a number of unique test and measurement challenges. Here we highlight some of the important elements of the emerging specification as it relates to design and test, and outline key considerations as this standard gains acceptance.

The typical desktop or laptop PC has a PCI Express bus at its core and has been the computing platform of choice for productivity and entertainment for the last 20 years or so. 350 million were sold in 2011. Now however, after several quarterly declines in PC sales and gloomy forecasts for the future, it’s clear the salad days are over for PCs as mobile devices like smartphones and tablets take over. 

But it’s hard to imagine the PC fading away without a fight. Instead what’s likely to happen is the emergence of a new class of device that combines the performance and rich functionality of a PC with the portability and battery life of mobile. Such a compromise-free device will incorporate backbone PC interfaces such as USB and PCIe, bringing the massive PC ecosystem along for the ride into the fast-growing mobile universe.

The first step occurred with the release of the SuperSpeed Inter-Chip (SSIC) specification in June 2012, which enabled USB 3.0 to connect chips using M-PHY physical interface.  A similar step now is taking shape with M-PCIe efforts to combine the upper layers of PCIe with M-PHY to bring PCIe hardware and software functions to mobile devices. As shown in Figure 1, the multi-layered M-PHY specification offers a single standard, powerful enough to address existing and future mobile device requirements, and yet is flexible and configurable enough to accommodate a range of technologies.

Figure 1. M-PHY provides a single standard that can accommodate a range of technologies.

Essentially, M-PCIe extends PCIe’s I/O benefits to mobile devices, such as tablets and smartphones. In many respects, it combines the best of both PCI-SIG and MIPI. PCIe is supported in all major operating systems, has a good power management architecture, provides a well-developed software model, and offers robust discovery and configuration.

For its part, M-PHY offers lower power than the PCIe PHY, better electromagnetic interference (EMI) characteristics, and independently scalable receive and transmit channels. This is important for mobile since users typically download more than they upload. M-PHY handles this workload well, and with M-PCIe that benefit is extended to PCIe.

The core premise behind M-PCIe is simple: replace the PCIe PHY with M-PHY and retain the rest of the PCIe protocol stack including data link layer, transaction layer, and software layers. Considered an engineering change notice to the PCIe 3.0 bas specification, the M-PCIe specification consists of just 60 pages compared to about 1,000 for the full PCIe 3.0 specification.  It does not cover such specifics as form factor and doesn’t call for any modifications to PCIe or M-PHY.

That isn’t to say that integrating PCIe and M-PHY is a trivial task. To start with, the PCIe protocol itself is quite complex. Layering a different PHY underneath the existing PCIe stack required the resolution of several issues including mapping of M-PHY power states to PCIe states, error handling, and link discovery and configuration processes.

One notable area, for instance, is link training. PCIe has three generations, each specified by the rate of transfers per second. These include Gen 1.0 at 2.5 GT/s, Gen 2.0 at 5 GT/s, Gen 3.0 at 8GT/s, and the forthcoming Gen 4.0 at 16GT/s.  In contrast, M-PHY has three gears.  Gear 1 operates between 1.25-1.45 Gb/s, Gear 2 at 2.5-2.9 Gb/s, and Gear 3 at nearly 6 Gb/s. M-PHY supports two independent reference clock rates, 19.2 or 26 MHz, which varies considerably from PCIe’s 100 MHz distributed clock. In terms of encoding, M-PHY uses an 8b/10b scheme at all rates or gears as does PCIe Gen 1.0 and 2.0. PCIe 3.0, however, uses a more efficient 128b/130b encoding scheme.

The M-PCIe specification is currently at revision 0.7a and is anticipated to be released in Q4 2013. The M-PCIe specification is now available on the PCI-SIG website. Implementers of M-PCIe technology must be members of both PCI-SIG and MIPI Alliance in order to leverage member benefits, including access to licensing rights and specification evolutions.

Coming up to speed on test
Looking at the test requirements, M-PCIe in some respects represents a less radical step than going from PCIe 3.0 to PCIe 4.0, for instance, since the speeds in M-PHY are somewhat reduced. Still, for designers coming to M-PCIe either from the mobile side or for PCIe side, there will be a period of adjustment to learn the ins and outs of the new specification.

One obvious area is that designers should be prepared to see a more assertive role for the PCI-SIG in managing compliance testing. If PCI-SIG stays true to form, it may require the use of specialized electrical text fixtures such as the Compliance Base Board used for testing PCIe add-in cards. To date, MIPI Alliance has tended to be more open.

For PCIe designers already familiar with verification and characterization of high-speed serial links, M-PHY’s changeable gears, terminations and amplitudes will introduce a new set of testing challenges.  For mobile designers, the high-speed serial standards will further increase the importance of maintaining the signal integrity of links with more emphasis on timing/jitter and noise. Receiver stress testing is also a requirement.

Compared to buses like PCIe that are essentially on or off, M-PHY is much more dynamic with multiple power modes. This dynamic nature makes protocol capture challenging for FPGA-based signal decoding. The use of an oscilloscope with appropriate decode, trigger and search capabilities will be necessary to verify the consistency of bus performance over time. Such tools as shown in Figure 2 enable trigger and search on control characters, symbols, patters and character error or disparity errors.

Figure 2. Oscilloscope-based M-PHY decode, trigger and search aids debugging.

Although data rates are bound to continue to increase, currently the fastest M-PHY High Speed (HS) signaling mode is Gear 3 which operates at 5.83 Gbps. At this speed, you’ll need an oscilloscope with at least 20 GHz bandwidth. Given the compact physical layouts used in mobile devices, signal access will be an ever-present challenge and you’ll need differential SMA-based probes.  Similarly, you’ll need the ability to de-embed interconnect loss. 

On the receiver side, electrical compliance tests will continue to be accomplished using an arbitrary waveform generator as the signal source and bit-error-rate tester (BERT) or a high-speed real-time oscilloscope functioning as a bit-error detector. An arbitrary waveform generator (AWG) also lets you automate receiver and compliance testing for faster time-to-market and improved test accuracy and consistency.

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