3D chip/package/PCB co-design optimizes systems: Product how-to

-September 12, 2015

Three independent design processes – chip, package, and PCB – are typically required for the latest electronic products which utilize increasingly complex systems on chip (SoCs) and multiple chips in single packages. Today these three processes are typically carried out with point tools that require time-consuming and error-prone manual processes to link the three processes. But an integrated 3D chip/package/board co-design environment provides the ability to holistically optimize the package, board, and IC design to a greater degree than was possible in the past by considering the system-level impact of each design decision. Designers can optimize routability via pin assignment and I/O placement to minimize layer counts between the package, chip, and board. The new approach makes it possible to deliver more functional, higher performing, and less expensive products to market in less time.

 

Limitations of traditional design methods

Traditional system design relies on tools that address the IC, package, and PCB in stand-alone environments. These flows lack system-level planning, visualization, design, and analysis. Design databases used in planning are not interoperable with databases used for review and analysis so it is difficult to guarantee that decisions made during planning are carried through to the final product. In traditional 2D component-specific design tools, co-design is challenging because designers typically only have a view of their own component. The file interchange formats used to exchange data between these environments are often antiquated and deficient, missing useful design data or are proprietary and not broadly supported. No tools exist in traditional flows to integrate all the components of a system and maintain both the electrical and mechanical database information and thus provide a realizable co-design environment. 

This approach was acceptable in the past as most complex systems had large form factors (servers, PC towers, large machinery) and package and substrate costs were a negligible part of the overall system cost. With increasing functionality, tighter cost constraints, and the decreasing form factor of today’s products (portables, wearables and automotive), components need to be tightly coordinated with each other so that pin assignments can be optimized for small size and minimum layer count substrates.

With the lack of tool integration, but increasing design requirements, companies have reverted to workarounds such as using spreadsheets and generic office productivity tools to perform planning and feasibility studies and to define the tool interfaces and data transfer. These files are typically internally developed and have to be internally maintained and manually manipulated to interact with the tools in the flow. They suffer from limitations in the information they provide due to restrictive file input formats to the EDA tools. They are subject to problems such as design planning data that cannot be automatically correlated with final design output data, and pin assignment data that is limited to simple information like basic net and position information. Inter-component optimization of pins, I/Os, placement and routing is infeasible due to the lack of a central design environment and the use of manual feedback mechanisms for system data.

PCB product design vendors have begun to introduce tools to address these challenges leveraging traditional databases to cut development costs. However, these new tools are limited to 2D environments or to one package and one PCB due to the inflexibility imposed by the traditional database structures. The need to switch back and forth between 2D and 3D views requires file conversions between the traditional 2D design database and the newer 3D viewer database which slows the design process, increases uncertainty in translation accuracy and limits design insight.

With smaller product form factors, the need arises to check the ECAD design footprint with the mechanically designed enclosure and to perform multi-physics analysis considering the enclosure. With enclosures increasingly migrating from orthogonal to tighter, more complex curved shapes, 3D views are required as 2D views are overly restrictive and cannot accurately represent the system. Traditional flows separate ECAD and MCAD designs with little opportunity for cross flow analysis. Electronics industry-specific design automation in MCAD flows has been difficult to achieve due to their general-purpose nature. 

 

Emergence of system-level 3D co-design

A new generation of system-level 3D co-design tools addresses these challenges by providing an environment for system design that integrates planning and final design at the system level and on PCBs, ICs, and mechanical enclosures. These databases are brought into a single view so each person working on the project can see their piece of the puzzle in context of the full product. Engineers can do system-level design, full package design, full PCB design, interposer design, and optimize the RDL (redistribution layer) routing and die bump placement for ICs design in a single user interface. The mechanical enclosure design can be checked against the final ECAD form factor (PCBs, packages, and ICs) dimensions to ensure fit and clearance. An integrated design-for-manufacturing tool makes it possible to verify the design to vendor technology-specific manufacturing checks for fabrication and assembly during layout. Documentation can be automatically generated for sign off and manufacturing. Push button integration with multi-physics analysis tools ensures design data is transferred efficiently and quickly to achieve quick turnaround. 

 

Co-design of IC and package with RDL and package fan-out escape routing

This integrated co-design environment permits a unique design approach unavailable in discrete or limited 2D tools. For example, engineers can perform a feasibility study of different numbers of package layers while considering the routing on the RDL on the IC side and the escape route on the PCB side in a single design view. The ability to conduct system-level co-design of the chip and package makes it possible to optimize bump and ball placement, I/O placement and pin assignment to lower chip, package and PCB layer counts even in non-traditional structures with routing complexity in both vertical directions like PoP, SiP, Chip-scale Packaging, and 3DIC/3D packaging. Automatic routing of the chip RDL and package escape permits rapid path finding feasibility, improves completion times and allows users to optimize die bump placements. The benefits include reducing RDL, interposer/substrate and package layer count while optimizing signal performance and improving time to tape-out.

 

Real-time swap between PCB design (top) and package design (bottom) for improved routability and performance

Viewing the IC, package and PCB simultaneously in one view helps engineers optimize pin assignment and avoid connectivity errors, reducing design time. If a designer needs to perform package/IC bump assignment, he or she can view the effects on the rats nest at the PCB level. Or if the designer has to make automatic or interactive pin-swaps at the board level to improve PCB routability, he or she can observe the potential impact at the package and IC level. The pin swap operation is automatically communicated between the package and PCB databases, eliminating the need for CSV or other neutral files to communicate the change. The tool also enables multiple engineers to work on a single substrate while protecting edits from the other engineers. If a designer needs to make a pin swap in a locked package design, he or she can send a notification that the other engineers can accept or reject as an ECO.

Intelligent PoP and SiP design

Using this technology, multiple ICs can be imported into the co-design environment and connected together. The 3D, multi-design environment more intelligently manages the routing interdependencies of complex packages such as PoPs and SiPs. This new approach provides focused design rule checks for SiPs with real-time 3D design and support for complicated bond wire placement of stacked LSIs. Engineers can use the co-design environment to ensure that bond wires meet the spacing requirements at any angle, and that the 3D bond wire profile meets the manufacturing specification.

 

Managing complex 2.5/3D IC designs with TSVs

This new approach greatly improves the floorplanning and routing of TSV-based designs such as 3DIC stacked chips and silicon interposers. Engineers can import existing databases (from OpenAccess, GDS or LEF/DEF files) or use the design environment to generate TSVs. Automatic or manual routing can be executed using imported or manually generated manufacturing and design rules. Preplaced TSVs can be automatically routed while unplaced TSVs can be placed and routed. The 3D environment supports large datasets and allows designers to see complex escape and routing structures

Verify signal performance with integrated signal and power integrity analysis 

As changes are made at any level of the system, designers can view the effects from a signal integrity, power integrity, or thermal point of view. Multi-discipline, multi-physics analysis can be performed with best-in-class solutions from solution providers such as Keysight Technologies, ANSYS, AWR, CST, and Synopsys. The co-design environment enables signal traceability across the complete system. Signal paths can be reviewed and analyzed as they cross design and component boundaries from drivers through the system interconnect to receivers. Intelligent and integrated schematic- or layout-based simulation environments support multiple design flows.

 

Conclusion

Chip/package/board co-design provides a unified design approach that enables designers to consider the system-level impact of each design decision to reduce design costs, improve performance, reduce uncertainty, and accelerate schedules. Designers can consider IC/package/PCB issues concurrently to design well integrated products with optimal signal performance while reducing RDL, interposer/substrate, and package layer counts to reduce costs and time to tape-out.

 

Also see:

 
Want to learn more? Attend DesignCon 2016, the premier conference for chip, board, and systems design engineers. Taking place January 19-21, 2016, at the Santa Clara Convention Center, DesignCon will feature technical paper sessions, tutorials, industry panels, product demos, and exhibits. Register here.

 
 
 

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