Avoid problems with multiple DC-DC converters

-May 05, 2014

Most electronics today requires multiple supply voltages – four or more rails is not uncommon. But if you're using multiple, unsynchronized DC-DC converters, you've not only got a sub-optimal design, you're asking for trouble. This Design Idea solves both problems.

Why trouble? I have firsthand experience of multiple power frequencies used in a system which also included sensitive analog electronics. Under certain conditions, difference frequencies (e.g., 10kHz, if one switcher was running at 250kHz, and another at 260kHz) would show up in high-impedance analog sections. Not good.

Why sub-optimal? The input filter capacitors of a DC-DC converter are almost as critical as the output caps. These capacitors, be they large ceramics, or high-performance electrolytics, are not cheap. In a multiple-converter system, each converter will need a full complement of input capacitors. But if we synchronize and stagger the channels, input capacitors can be "shared" to some extent. The cost and size of the circuit presented here could easily be less than the cost & size of the eliminated caps. The improved performance is a free bonus.



Figure 1  Example DC-DC converter with SYNC input

Fortunately, many IC and modular converters these days have a SYNC input pin. The LM2747 is a good example of a suitable controller IC. The synchronizer is a CMOS decoded counter, such as the 4017/4022, or 74HC4017. This is driven with a clock signal equal to the converters' operating frequency times the number of converters. Connect the first unused counter output to its RES/MR (master reset) pin to set the correct count length.



Figure 2  Synchronization circuit wired for four converters

This design can easily be implemented in programmable logic too, potentially making it totally free. Of course, the switchers won't be synchronized as the power is ramping up. The synchronization logic will need to reach its operating voltage, and the converters themselves may have a small sync-up delay. If an FPGA is used for control, it may also require time to initialize.


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