Optimizing snubber design through frequency-domain analysis
Switching voltage regulators are used nowadays in almost every electronic device, from smartphones to cars. Performance has been pushed to the limit, efficiency has reached the high nineties, and size has shrunk thanks to deep circuit integration. A few decades of research and development has also made voltage regulator design a well-understood topic with tens of different topologies available to satisfy everyone’s needs.
Regardless of the topology adopted, carefully designed placement and layout is crucial for the proper operation of the regulator. Minimizing the parasitic components due to layout is a critical aspect of the design process because of the high-voltage, high-current signals that switch at few hundreds of kHz—or more—on the board. Here, even the smallest parasitic components can cause potentially troublesome oscillations that can create electromagnetic interference (EMI) and, over time, stress the IC. Even if a proper layout is a must to limit the parasitic, sometimes, because of space constraints, mechanical limitations, tight specs or extreme operating conditions, a snubber network is one technique to limit the oscillations created by the remaining parasitic components.
The design of the snubber circuits requires a fine-tuning of all its components since, as explained in the next paragraph, increasing the strength of the snubber reduces the voltage ringing at the expense of converter efficiency. Recommendations provided in most of the traditional application notes on the market take this topic quite lightly, as if converter efficiency was not a key selling point.
The recommended values are the same regardless if the application fails the specs by a couple of volts or needs to cut the ringing by 50%. Clearly, this “one-value-fits-all” approach is not optimized and cannot be used to design high-efficiency, best-in-class products.
The analysis proposed in this article focuses on the RC snubber circuit and provides a clear and rigorous way to find the optimal values for its components based on the actual needs. The first section describes the strengths and weaknesses of RC snubbers, along with a rigorous way to measure the parasitic components. The following section describes how the value of the optimum snubber resistor is mathematically derived using the analysis in the frequency domain, leading to a simple—yet rigorous—equation. Next, numerical simulations are used to derive the equation to select the best snubber capacitor. Finally, a few examples and comparison with traditional methods show the strength of the proposed analysis. The conclusion conveys a step-by-step procedure to use this method.The RC snubber
Figure 1 shows the typical application of an RC snubber circuit applied to a synchronous buck converter. In the ideal application, when the low-side (LS) FET opens and the high-side (HS) FET closes, the voltage on the switching node (Vx) rises from low, slightly below GND due to the LS FET body diode conduction during the dead time, to high, the input voltage.
Figure 1: RC snubber circuit applied to a synchronous buck converter.
When real-world parasitic components (resistance, inductance, and capacitance) are taken into account, the voltage on the Vx node starts oscillating during the commutation (red curve in Figure 2), stressing the device above the design limits and causing EM interference and noise injection in the adjacent circuits.
Figure 2 Effect of the parasitic components on the switching node in a buck converter.
Acting as a load at the proper frequency, the RC snubber network placed on the Vx node damps the oscillation. Its effectiveness—in terms of the amount of ringing reduction—improves with the value of the snubber capacitor (Figure 3), and its upper limit should be determined by the efficiency drop associated with it .
Figure 3 Effect of the snubber on the Vx ringing. The higher the snubber capacitance, the stronger the ringing attenuation.
During every switching cycle, Csnb must be charged and discharged, dissipating an average power equal to:
The bigger Csnb, the higher the energy that goes into charging and discharging the snubber, reducing the overall VR efficiency.
The circuit in Figure 4 models the parasitic components and the snubber network under the conditions described above.
The HS FET is closed and represented with its RDSon resistance. The LS FET is open instead, and contributes only with its output capacitance. The parasitic inductance is mainly due to the PCB traces, package, and pins.
To summarize the components in Figure 4:
- R1 is the sum of the HS FET RDSon and the trace resistance from the input voltage (the closest input capacitor) to the Vx node;
- L1 is the parasitic inductance introduced by the PCB trace, package, soldering, and pins;
- C1 is dominated by the output capacitance of the HS and LS FETs
Figure 4 Model of the electrical circuit including the parasitic components and the snubber circuit.
Given the parasitic nature of these components, and the fact that their value depends on many factors (including PCB, soldering, placement…), their values must be measured and should not be estimated based on datasheets values.
Here’s a simple and accurate method to measure R1, C1, and L1. The Vx voltage of the circuit in Figure 4 (with the exclusion of the snubber components) is described by the following equation:
Adding an additional capacitor of known value—Cadd—in parallel to C1 shifts the angular frequency to a lower value ωr2.
Figure 5 Voltage on the ringing node.
Figure 5 shows the experiment with Simplis simulations. ωr1 and ωr2 can be measured from the waveforms as:
And Cadd is a known quantity (6nF in the example) since it was added during the test.
Knowing these values, the above system of three equations with three unknowns can be solved as:
Once the values of these parasitic components are determined, the design of the snubber can start. In this paper, the values of R1, C1 and L1 will be assumed to be the following unless otherwise noted.
R1 = 10mΩ
C1 = 0.5nF
L1 = 1.5nH