Delay line eases Spice dead-time generation

-March 02, 2000

Generating complementary clock signals in a Spice simulation is an easy task. However, this task gets much harder if you need to introduce some dead time into the signals. This difficulty is especially true when you're dealing with a variable-pulse-width-modulated switching cycle. In fact, you need to insert a dead-time interval between the switching of any two power devices in series, such as bridge or half-bridge designs that use MOSFETs and switch-mode power supplies and that implement synchronous rectification. The dead time prevents any cross-conduction, or shoot-through, between both switches and helps to reduce the associated losses.

The circuit in Figure 1a overcomes this typical Spice problem. The input clock drives two delay lines that feature the same specifications. When the clock goes high, one input to X2's AND gate is also high. However, because of the delay line, the other input stays low for the given dead time. When both inputs are high, the output is a logic one (Figure 1b).

When you generate models in a proprietary syntax, the translation process to another platform is usually painful. However, thanks to common Spice3 primitives, such as the delay line, T, the translation of this generator is easy to implement. The netlists in Listing 1 and Listing 2 implement a half-bridge driver with a floating upper output in IsSpice4 (Intusoft) and Pspice (OrCAD), respectively. The BL (Listing 1) and EBL (Listing 2) inline equations implement the AND gates of Figure 1a, which saves you from using a subcircuit arrangement. Typical applications include half-bridge drivers and synchronous rectifiers. You can easily tailor any output polarity by reversing the corresponding Spice element. For instance, if you want to reverse the upper generator, BU1, in Listing 1, simply replace the lineV= (V(CLK)>800M)& (V(TD1)>800M) W {VHIGH} : {VLOW} withV= (V(CLK)>800M) &(V(TD1)>800M) W {VLOW} : {VHIGH}.

Figure 2a portrays a typical application of the dead-time generator in a simplified half-bridge driver, and Figure 2b shows the corresponding IsSpice4 waveforms. (DI #2490)

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