Clock multiplier circumvents PLL

-May 13, 1999

Using a standard PLL circuit, such as the CMOS 4046B with some passive components, is a well-known way to design a clock multiplier. Unfortunately, using a PLL in a digital circuit has two disadvantages: It takes a long time for the circuit to reach a stable output frequency, and the frequency-drift compensation has a complex design.

An alternative clock-multiplier approach uses simple combinatorial logic and a delay line (Figure 1). By taking into account the propagation delays in combinatorial logic and the fact that most logic designs are edge-triggered, the circuit can multiply by 2, 3, 4, and potentially beyond. You can use this technique to increase the system clock speed and maintain a low-frequency clock for the rest of the circuit, thereby helping to reduce EMI and cost in high-speed logic designs. Also, the circuit exhibits a very fast start-up. This approach is common in modern ?P architectures that use clock-doubling techniques to achieve better performance at low costs.

In place of the silicon delay line, you could use standard CMOS logic. However, the differing propagation delays for high-to-low and low-to-high transitions (tpdHL[not equal]tpdLH) presents a problem. A standard delay line with fixed and known delay taps is preferable.

The circuit in Figure 1a uses a Dallas Semiconductor ( DS1010-400 delay line, which has 10 built-in fixed delays of 40 nsec, to implement a 2X, 3X, and 4Xclock multiplier that operates from an external 1.0416-MHz clock. This design requires XOR gates with short propagation delays, such as advanced-bipolar or fast CMOS gates with propagation delays of less than 10 nsec, so that the XOR-gate delays are negligible.

The circuit works by using the XOR gates to perform a phase comparison. These gates monitor the difference between the incoming clock signal and the delayed clock signals. First, the circuit shifts right, or delays, the signal to be multiplied: once for 2X, twice for 3X, three times for 4X, and so on. Then, because an XOR gate sits between the source and the delayed signals, the result of the XOR operation is the signal multiplied by 2, 3, and 4. The resultant clock signals have the same duty cycle as the incoming signal (Figure 1b). Figure 2 shows the internally delayed clock signals that are necessary to produce the 2X, 3X, and 4X clocks.(DI #2344).

Loading comments...

Write a Comment

To comment please Log In