Product How-To: Solar power anti-islanding and control

Lawrence Meares, Intusoft -August 07, 2012

When connecting a solar power source to the AC mains, it is possible to supply power to the local area in the event of a power outage. While your neighbors might be happy with this behavior, it is a hazard to utility workers attempting to restore power. This effect, called islanding, must be eliminated in the grid-tie inverter design. If a phase-locked oscillator synchronizes the inverter output to the line; then a power outage results in the inverter synchronizing to itself. The frequency will then drift out of tolerance, signaling a power outage. This article describes how to achieve this design goal using a digital controller and Intusoft’s DSP Designer to simulate the digital design and generate some of the necessary code.

Testing the anti-islanding feature: The U.S. National Electric Code, NEC, defines a test using a resonant circuit at the inverter input, which has a Q of 3 at the inverter maximum power level. The circuit is adjusted so that removal of the mains power will not be detected instantly. The inverter will not be overloaded so that in the absence of special detection circuitry, the solar power will electrify the local grid.

Figure 1. Block diagram.

Block Diagram: Figure 1 is a block diagram of the line synchronizing system. Notice that the operation of this system doesn’t depend upon the NEC test condition. The idea is to synchronize the inverter using a phase-locked-loop, PLL [1]. If the grid is only supplied by the Inverter, then no error signal is developed at the phase detector and the frequency will drift toward zero. When it gets below some pre-defined limit, the Inverter is shut off until mains power is restored; at which time the PLL syncs up and solar power generation is resumed. The logic gets a bit more complex when a battery backup is included, requiring a switch to isolate the grid from the backup loads. The traditional PLL controller consists of a multiplier to detect the phase error, followed by a PI controller. The large second harmonic signal must be filtered to reduce non-linearity in the voltage-controlled oscillator, VCO, and to allow meaningful measurement of phase error, frequency and line voltage.

Theory: Phase Locked Loops belong to a class of nonlinear circuits that have been studied extensively [1]. When phase detection is accomplished using a multiplier, the second-order nonlinear equation can be solved explicitly. PLLs are used in communications circuits, such as Global Positioning Systems (GPS) to make a narrow band filter centered about the carrier frequency. The noise filter, while not part of the lower frequency phase control loop, is used to eliminate out of band noise. For this problem, the carrier signal is the 60 Hz mains and it is not particularly noisy, although it may have some harmonic distortion. The mains frequency is tightly controlled so that various generators on the grid can be easily synchronized. The main signal to be eliminated by the noise filter is the double frequency, 120 Hz, component that is output by the phase detector. The digital filter used here reduces this unwanted signal by nearly 40 dB. The average value of the mains fundamental is detected using the quadrature signal from the VCO, which is synchronized to the mains. The following logic is used to indicate that synchronization has begun; that is, it sets a software flip-flop:

VlinAvg > 78 Volts (86 VRMS) and
abs(frequency-60) < 1) and
(abs)phase < .025 radians (1.4 degrees)

The flip-flop is reset when:

abs(frequency-60) > 2) or
VlinAvg < 72 Volts (79 VRMS)

The first reset condition accomplishes the anti-islanding function when the Inverter is supplying power to the grid, and the second condition signals a grid power loss when in standby. The sine output of the VCO is used to switch synchronous rectifiers used to transfer power between the grid and the backup system when a backup battery is present. Backup systems require transferring power in either direction to account for load phase shift (motors) and battery charging, so the use of synchronously switched rectifiers is required.

Selecting Sample Rates: High sample rates give improved accuracy but require longer digital word lengths. Constraining word lengths to 16 bits allows the use of very low cost and low power digital controllers. For this problem, the sine-cosine generator is run at the Inverter switching frequency, which is 25 kHz, a 40 microseconds. That resolves the line voltage to about 2.5 Volts at zero crossing for a 120 Volt RMS line. But the PLL can be sampled at a much lower rate, greater than or equal to 10 times its loop bandwidth. The communication system for this DSP runs at 1 kHz, which meets this criteria.

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