An efficient RDL routing for flip-chip designs
Engineers use a redistribution layer (RDL) in flip-chip designs to redistribute I/O pads to bump pads without changing the I/O pad placement. However, traditional routing capacity may be insufficient to handle sizable designs, in which the RDL may be very congested and especially when there is a less-than-optimal I/O-bump assignment. As a result, routing may not be completed within a single layer even with manual routing.
As demand for more input/output (I/O) increases, traditional wire bond packaging may not effectively support thousands of I/Os. Flip-chip assembly is commonly used in place of wire bond because it reduces chip area while supporting many more I/Os. It also greatly reduces inductance, allows high-speed signals, and possess better heat conductivity properties. The flip-chip ball grid array (FCBGA) is also growing in popularity as an alternative methodology for high I/O count chips.
Figure 1. Flip chip cross section: Signal traces travel through three interfaces including RDLs.
The redistribution layer (RDL) is the interface between chip and package for flip-chip assembly (Fig. 1). An RDL is an extra metal layer consisting of wiring on top of core metals that makes the I/O pads of the die available for bonding out other locations such as bump pads. Bumps are usually placed in a grid pattern and each one is molded with two pads (one on the top and one on the bottom) that are then attached to the RDL and package substrate respectively. The RDL, therefore, serves as the layer connecting I/O pads and bump pads.
Figure 2. Free-assignment (FA) and pre-assignment (PA) are two pad assignment methods. Peripheral-I/O (PI/O) and area-I/O (AI/O) are two flip-chip structures.
Flip Chip Structures & Pad Assignments
Previous research has identified two flip-chip structures and two pad assignment methods, both shown in Fig. 2. Free-assignment (FA) and pre-assignment (PA) are two pad assignment methods. Peripheral-I/O (PI/O) and area-I/O (AI/O) are two flip-chip structures.
The two pad assignment methods are defined by whether or not the mapping between bump pads and I/O pads has been given as input. For FA problems, each I/O pad is free to assign to any bump pad, so assignment is considered together with routing. For PA problems, each I/O pad must connect with a specified bump pad, thus solving complex crossing issues. PA problems are more difficult than FA problems but, at the same time, are more convenient for designers.
Two flip-chip structures represent patterns of I/O placement. AI/O and PI/O challenges place I/Os in the central area and on the periphery of die respectively. PI/O is more popular today because of its simplicity and low design cost, although AI/O theoretically provides better performance.
An example of PI/O is shown in Fig. 3. The green rectangles on the periphery are I/O pads. The red and yellow circles are power and ground bumps, while the blue circles are signal bumps. Some power/ground bumps, located in the center of die, are sorted by mesh type. Signal bumps are sorted by grid type.
Figure 3. RDL top view. Bump pads in a grid pattern and I/O pads on the periphery.
All aforementioned works focus on single-layer routing. They restrict routes to one metal layer on which every net must be routed. The common objective is wire-length minimization. The optimization schemes are done under a prerequisite that routability is 100%. This has proven to be very successful for each type of RDL routing problem, providing that a single layer solution exists.