Shaving power/area with merged logic in SoC designs
Implementing the duplicated logic concept
Figure 3 is a conventional circuit where two flip-flops have been merged to provide the same functionality as needed and a select signal ‘S’ has been introduced which would control the clock of flip-flop 1 and flip-flop 2.
The need for a sequential element/flip-flop in a design is to store the present state of design. This element itself consists of a master stage and slave stage. It is the slave stage in which the data is eventually stored and transferred to the next element of the design. Master acts as a gate to permit only latching of that data in the flip-flop, which is available at the clock edge. Area consumed is 2 FF + 1 MUX + 2 AND + 1 INV gate area.
Figure 3. Merged (conventional circuit) flip-flop for implementing duplicated logic
In the proposed flop, the two flops are working on the alternate edges to capture the data. So, we can very easily share a common master for the two flops. This master can operate at the original clock to the flop (as shown in Figure 4) while the slave stages at the clocks determined by the select signal. As can be seen in the Figure 4, at the first active clock pulse, the master will accept the data and transfer it to the slave 1 (selected by select ‘S’ signal). The data will continue to reside in slave 1 till the 3rd clock pulse. At the second active clock pulse, master will again sample the data and transfer it to slave 2 (selected by select ‘S’ signal). This data will continue to reside in slave 2 till the 4th clock pulse. Figure 5 illustrates the associated timing waveform.
Figure 4. Proposed flip-flop for implementing duplicated logic
Figure 5. Timing waveforms for the proposed circuit