New test requirements for 40/100 GbE transceivers
As the latest generation of high speed communication standards comes together, two worlds have emerged. The first is the realm of Ethernet at 40 and 100 Gb/s speeds with traditional NRZ signaling. This is intended to meet the bandwidth requirements of low-cost LAN and metro networks, based on existing technologies. The other is to meet the need among carriers for higher-speed long haul links and incorporate new complex DP-QPSK optical signaling. For this article we will be addressing primarily Ethernet test requirements.
While many of the test procedures will be familiar to designers, the move to 40/100 GbE introduces a number of new test challenges including a new CFP (C form-factor pluggable) module, 25 Gb/s optical signaling, WDM channels that complicate testing and the use of many more channels and the associated problems with crosstalk. There are also a number of key new measurements including new scaled 25/28G masks, J2/J9 jitter measurements, stressed eye testing and frequency domain channel measurements.
New high-speed interfaces, transceivers
The IEEE 802.3ba standard specifies a set of high-speed transmission side interfaces as well as for the chip to module interconnect. These interfaces, which are designed to fit a range of applications and requirements, vary significantly in terms of such factors as power and complexity. For instance, applications involving shorter distances can use simpler, more cost-effective designs.
The CFP for both 100GbE and 40GbE are defined by a multisource agreement (MSA), providing an industry standard to support next generation Ethernet optical transceiver interfaces. The CFP MSA defines the form factor of a hot-swappable optical transceiver, as illustrated in Figure 1, supporting 40/100GbE and uses an electrical interface consisting of multiple 10G lanes. The optical module is connected to a PHY and a Media Access Control (MAC). The optical modules provide a 10 Gbps parallel differential electrical interface to connect with the components on the line card. Specifically, the optical module interconnects are referred to as XLAUI for the 40 Gb/s Attachment Unit Interface and CAUI for the 100 Gb/s Attachment Unit Interface.
Fig 1: The CFP includes a pluggable CFP modules and chip to module electrical interfaces (CAUI).
The main development focus currently is on 100GBASE-LR4/ER4 in which one fiber carries four 25G wavelengths or lambdas. For the short reach, the multimode 40GBASE-SR4 and 100GBASE-SR10 achieves the 40 Gb/s and 100 Gb/s, respective bandwidth with 10 fibers of 10G. Both the 4×25G and 4×10G schemes use a single mode fiber to give a 10-km reach with 40 km possible. On the electrical interface side, a system of 10 parallel electrical lanes, each carrying 10 GbE, provides a good mix of cost-effectiveness and flexibility.
The Physical Coding Sublayer (PCS) is responsible for tying multiple lanes together through striping or fragmentation techniques. This architecture is shown in Figure 2. The number of PCS lanes is usually the least common multiple of the number of electrical and optical lanes. Typically, 10×10G electrical lanes and 4×25G optical lanes; 20 virtual 5G PCS lanes are used in most CFP implementations. Including receiver and transmitter there are a total of 40 lanes.
Fig 2: The Physical Coding Sublayer provides 20 lanes, each as differential, for a total of 40 including receiver and transmitter.