PRBS generator runs at 1.5 Gbps
PRBS (pseudorandombinarysequence), or PN (pseudonoise), generators find a broad range of applications in digitaldata transmission (Reference 1). These circuits often comprise simple shift registers with feedback that can serve as test sources for serialdata links. As their name implies, the output sequence is not truly random and in fact repeats after 2^{N}–1 bits, where N denotes the shift register's length. Polynomial notation, in which the polynomial order corresponds to the shift register's length and, thus, the PRBS' period provides a convenient method of describing the sequence.
Communicationsequipment tests use certain standard polynomials. For example, x^{7}+x^{6}+1 yields a PRBS period of 127 bits, x^{23}+x^{18}+1 yields a period of more than 8 million bits, and x^{31}+x^{28}+1 yields a period that's 256 times longer. A PRBS with a longer period generally produces a greater variety of data patterns that more thoroughly check the transmission system's performance.
A simple shift register with feedback from an intermediate stage can generate a PRBS. The flipflops constituting the register must run at a speed equal to the transmission speed, which may pose a problem if you want to build a longperiod PRBS generator that runs at a gigahertz clock rate. A highspeed serializer such as Texas Instruments' TLK2201B, which runs at data rates as high as 1.6 Gbps, offers one potential solution to the problem. However, instead of accepting a PRBS in its natural fully serial format, the serializer accepts only 10bit portions at a time.
The circuit in Figure 1 illustrates a 31storder, parallelPRBS generator that delivers 10bit output segments and can easily adapt to other PRBS orders and output widths. To design the circuit, begin by drawing a diagram with 31 flipflops arranged in rows containing nominally 10 flipflops. In this instance, the design comprises four rows, with only one flipflop in Row 1. Figure 1 shows the timing relationships among the flipflops and the numbering convention.
Figure 1 This circuit implements a 10bit paralleloutput PRBS generator defined by the polynomial equation x^{31} + x^{28} + 1. To reduce clutter, the schematic shows only one of 10 exclusiveOR gates that generates the register’s feedback signals. A common clock source (not shown) drives all 31 flipflops’ clock inputs.
The resulting structure forms a parallel shift register, with the fourth row fed directly from the third row, the third fed from the second, and so on. Flipflops 10 through 2 in Row 2 and flipflop 1 in Row 1 receive their inputs from the feedback path. This arrangement ensures that flipflops in consecutive rows always deliver their outputs 10 time instants apart, and the generator's clock thus runs at onetenth the speed of an equivalent serialshiftregister PRBS implementation.
To determine the feedback signals, derive the equation that describes a standard—that is, serial—PRBS generator's output, which, for a polynomial of x^{31}+x^{28}+1, yields: y(n)=y(n–31) xor y(n–28). Using that equation, you can derive the equations that describe feedback signals fdbk1 through fdbk10. That is, fdbk1: y (n+9)=y(n–22) xor y(n–19), fdbk2: y(n+8)=y(n–23) xor y(n–20), ... fdbk10: y(n)=y(n–31) xor y(n–28). For example, feedback signal fdbk1 derives from the output of a twoinput exclusiveOR gate driven by the outputs of flipflops 22 and 19.
Listing 1 contains the VHDL code that implements the circuit of Figure 1 in either a CPLD or an FPGA device. Lines 15 through 18 define the parallelshift register, and lines 21 through 23 define the feedback circuit's construction. The circuit in this Design Idea fits into an XC3S50 Spartan 3 device from Xilinx, runs at a 150MHz clock rate, and drives a Texas Instruments TLK2201B serializer at 150 MHz through a 10bit interface. Xilinx's ISE 7.1i software compiled the circuit's VHDL files. Figure 2 displays an eye diagram for the serializer's output and confirms the circuit's operation at 1.5 Gbps. The compilation software predicts that the circuit should run at clock rates exceeding 300 MHz, but the TLK2201B limits operation to 150 MHz.
Figure 2 A pseudorandom sequence produces this eye diagram as measured at the output of a TLK2201B serializer that an FPGAsequence generator drives.
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