Advertisement
Advertisement

Two gates and a microprocessor form digital PLL

-April 14, 2005

You can use Microchip's low-cost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock range, phase differential, and loop gain, the digital-PLL engine and lock detector can extract clock and data information from noisy, short-range radio signals (Figure 1). When you construct it using a QFN-packaged microprocessor and discrete single-gate logic devices, the circuit occupies a pc-board area that's approximately as large as an aspirin.

Figure 1 This microcomputer-based digital-PLL circuit locks to signals over a 4- to 40-kHz range and requires a minimal number of components.

Figure 2 is analogous to a first-order analog PLL (Reference 1). With its associated period register, Timer 2 functions as a DCO (digitally controlled oscillator). When Timer 2's count matches the byte in its period register, the timer generates an interrupt. The microprocessor then computes a byte of information that writes to the period register to set the duration of the next half-period. In addition, the interrupt toggles an I/O port's output to produce square-wave signal-output frequency, which drives one input of the external XNOR (exclusive-nor) gate, IC1. The external input signal's input frequency drives the XNOR gate's remaining input to produce an output signal, which represents the phase difference, between the output and the input frequency. This XNOR-based phase detector provides good performance with noisy digital input signals.

Figure 2 An XNOR-gate phase detector provides good performance with noisy signals, and a microprocessor handles signal processing.

The phase difference signal's duty cycle remains linear over a 0 to 180° range of two same-frequency signals. Applying the phase detector's output along with clock-signal clock frequency to OR gate IC2 produces an output burst of 2-MHz clock pulses during each half-period interval of output frequency. The burst's length and the number of clock pulses it contains depend directly on the duty cycle or phase interval of the output frequency relative to the input frequency.

The circuit applies phase-difference pulses from IC2 to the internal prescaler associated with IC3's Timer 1, which divides them by a preset factor of one, two, four, or eight. During each of the output frequency's half-periods, Timer 1 accumulates (integrates) the prescaled pulses.

The interrupt-service-routine software for Timer 2 closes the loop and determines the digital PLL's key parameters. This routine comprises 19 instructions that execute in about 10 µsec when IC3's internal clock oscillator runs at 8 MHz. After each Timer 2 interrupt, the interrupt-service routine toggles the output frequency, checks for phase lock, and then divides the output of Timer 1 by two, making K equal to one, two, four, eight, or 16. The routine subtracts the resulting value from N0 and writes the difference to Timer 2's period register, which sets the length of the output frequency's next half-period. Although some interrupt-service-routine operations slightly modify the result, this count is typically as follows:

     EQUATION 1

For phase lock, the output-frequency half-period must equal the input-frequency half-period. The computed variable half-period count adjusts the output's frequency and phase. If the input frequency is within lock range, the variable count changes in the direction necessary to achieve and maintain phase lock between the input and the output frequency. As an example, assume that the input frequency is 10 kHz; the maximum clock-frequency cycle count for each output-frequency half-period, N0, is 110; the division factor for the clock-frequency count that represents the phase of the output frequency, K, is two; and the output frequency is phase-locked to the input frequency. The half-period of 10 kHz is 50 µsec, or 100 counts, when the clock frequency is 2 MHz. Substituting these values in Equation 1 and solving for the variable phase count yields a value of 20, which corresponds to a phase of 0.1, or 36°. Thus, with these parameters, the digital PLL's output frequency locks to the input frequency with a phase difference of 36°.

If the input frequency decreases, its half-period lengthens, and the variable phase count becomes smaller. According to Equation 1, after the division factor divides the variable phase count and you subtract it from the maximum half-period clock-frequency count, the half-period of the output frequency increases, lowering the output frequency and driving it toward a new match with the input frequency. If the input frequency increases, the reverse occurs.

Equation 2 defines the digital PLL's operation in phase-lock frequency, and design-selected system parameters:

   EQUATION 2

∼34≤N0≤255; K=two, four, eight, or 16; and 0≤Φ≤0.5, where f is the frequency, fCLK is the clock frequency, N0 is the maximum clock-frequency cycle count for each output-frequency half-period, Φ is the phase of the output frequency relative to the input frequency, and K is the division factor for the clock-frequency cycle count that represents the output phase of the output frequency relative to the input frequency. Adding a constant value of 2.5 to the output frequency's period count compensates for interrupt-service-routine operations that slightly affect the timing. The calculated value of phase-lock frequency is accurate to within ±1.5% over most of the PLL's usable range. Because the PLL comprises only digital circuits and software, operation with any combination of parameters is repeatable.

You can manipulate Equation 2 to solve for any variable in terms of the remaining four. To calculate the upper and lower limits of the lock range, set Φ at 0.5 and 0, respectively. To calculate the digital PLL's "center frequency," set Φ at 0.25, which corresponds to a 90° phase angle. In the previous example, maximum frequency is 13,408 Hz, center frequency is 11,204 Hz, and minimum frequency is 8989 Hz. The lock range is 13,408 to 8989, or 4419 Hz. Increasing K to 16 yields a maximum frequency of 9544 Hz a center frequency of 9266 Hz, a minimum frequency of 8989 Hz, and a lock range of 555 Hz.

Resolution of the DCO using Timer 2 establishes the time jitter of the output frequency relative to the input frequency. Depending on the integer count written to its period register, Timer 2 produces discrete frequencies for output frequency. When the input frequency falls between discrete output frequencies that two adjacent counts produce, the PLL switches between the counts to produce an averaged but jittery output-frequency signal at the same frequency as the input frequency. Using a relatively large value of N0 reduces jitter, whereas a smaller value increases jitter. To improve resolution and reduce jitter, you can increase the clock frequency to 5 MHz by configuring the microprocessor's on-chip oscillator to use an external 20-MHz crystal.

You can adapt the digital PLL's basic design to a variety of applications by modifying the software and extending the interrupt-service routine. For example, stopping updates to Timer 2's period register puts the PLL in "coast" mode. Other expansion possibilities include implementing more sophisticated lock-detection circuitry to determine whether the input frequency falls within a certain frequency range and making dynamic adjustments of the values of N0 and K for better performance. Click here to download Listing 1, which is the assembly-language source code, as well as the hex programming file for IC3.

Reference
  1. Gardner, Floyd M, Phaselock Techniques, Second Edition, Wiley-Interscience, 1979, ISBN 0-471-04294-3.

Loading comments...

Write a Comment

To comment please Log In

FEATURED RESOURCES