Two gates and a microprocessor form digital PLL
You can use Microchip's lowcost PIC16F818 microprocessor and a pair of gates to construct a digital PLL that can clean noisy digital signals over a range of 4 to 40 kHz. Featuring programmable lock range, phase differential, and loop gain, the digitalPLL engine and lock detector can extract clock and data information from noisy, shortrange radio signals (Figure 1). When you construct it using a QFNpackaged microprocessor and discrete singlegate logic devices, the circuit occupies a pcboard area that's approximately as large as an aspirin.
Figure 1 This microcomputerbased digitalPLL circuit locks to signals over a 4 to 40kHz range and requires a minimal number of components.
Figure 2 is analogous to a firstorder analog PLL (Reference 1). With its associated period register, Timer 2 functions as a DCO (digitally controlled oscillator). When Timer 2's count matches the byte in its period register, the timer generates an interrupt. The microprocessor then computes a byte of information that writes to the period register to set the duration of the next halfperiod. In addition, the interrupt toggles an I/O port's output to produce squarewave signaloutput frequency, which drives one input of the external XNOR (exclusivenor) gate, IC_{1}. The external input signal's input frequency drives the XNOR gate's remaining input to produce an output signal, which represents the phase difference, between the output and the input frequency. This XNORbased phase detector provides good performance with noisy digital input signals.
Figure 2 An XNORgate phase detector provides good performance with noisy signals, and a microprocessor handles signal processing.
The phase difference signal's duty cycle remains linear over a 0 to 180° range of two samefrequency signals. Applying the phase detector's output along with clocksignal clock frequency to OR gate IC_{2} produces an output burst of 2MHz clock pulses during each halfperiod interval of output frequency. The burst's length and the number of clock pulses it contains depend directly on the duty cycle or phase interval of the output frequency relative to the input frequency.
The circuit applies phasedifference pulses from IC_{2} to the internal prescaler associated with IC_{3}'s Timer 1, which divides them by a preset factor of one, two, four, or eight. During each of the output frequency's halfperiods, Timer 1 accumulates (integrates) the prescaled pulses.
The interruptserviceroutine software for Timer 2 closes the loop and determines the digital PLL's key parameters. This routine comprises 19 instructions that execute in about 10 µsec when IC_{3}'s internal clock oscillator runs at 8 MHz. After each Timer 2 interrupt, the interruptservice routine toggles the output frequency, checks for phase lock, and then divides the output of Timer 1 by two, making K equal to one, two, four, eight, or 16. The routine subtracts the resulting value from N_{0} and writes the difference to Timer 2's period register, which sets the length of the output frequency's next halfperiod. Although some interruptserviceroutine operations slightly modify the result, this count is typically as follows:
EQUATION 1
For phase lock, the outputfrequency halfperiod must equal the inputfrequency halfperiod. The computed variable halfperiod count adjusts the output's frequency and phase. If the input frequency is within lock range, the variable count changes in the direction necessary to achieve and maintain phase lock between the input and the output frequency. As an example, assume that the input frequency is 10 kHz; the maximum clockfrequency cycle count for each outputfrequency halfperiod, N_{0}, is 110; the division factor for the clockfrequency count that represents the phase of the output frequency, K, is two; and the output frequency is phaselocked to the input frequency. The halfperiod of 10 kHz is 50 µsec, or 100 counts, when the clock frequency is 2 MHz. Substituting these values in Equation 1 and solving for the variable phase count yields a value of 20, which corresponds to a phase of 0.1, or 36°. Thus, with these parameters, the digital PLL's output frequency locks to the input frequency with a phase difference of 36°.
If the input frequency decreases, its halfperiod lengthens, and the variable phase count becomes smaller. According to Equation 1, after the division factor divides the variable phase count and you subtract it from the maximum halfperiod clockfrequency count, the halfperiod of the output frequency increases, lowering the output frequency and driving it toward a new match with the input frequency. If the input frequency increases, the reverse occurs.
Equation 2 defines the digital PLL's operation in phaselock frequency, and designselected system parameters:
EQUATION 2
∼34≤N_{0}≤255; K=two, four, eight, or 16; and 0≤Φ≤0.5, where f is the frequency, f_{CLK} is the clock frequency, N_{0} is the maximum clockfrequency cycle count for each outputfrequency halfperiod, Φ is the phase of the output frequency relative to the input frequency, and K is the division factor for the clockfrequency cycle count that represents the output phase of the output frequency relative to the input frequency. Adding a constant value of 2.5 to the output frequency's period count compensates for interruptserviceroutine operations that slightly affect the timing. The calculated value of phaselock frequency is accurate to within ±1.5% over most of the PLL's usable range. Because the PLL comprises only digital circuits and software, operation with any combination of parameters is repeatable.
You can manipulate Equation 2 to solve for any variable in terms of the remaining four. To calculate the upper and lower limits of the lock range, set Φ at 0.5 and 0, respectively. To calculate the digital PLL's "center frequency," set Φ at 0.25, which corresponds to a 90° phase angle. In the previous example, maximum frequency is 13,408 Hz, center frequency is 11,204 Hz, and minimum frequency is 8989 Hz. The lock range is 13,408 to 8989, or 4419 Hz. Increasing K to 16 yields a maximum frequency of 9544 Hz a center frequency of 9266 Hz, a minimum frequency of 8989 Hz, and a lock range of 555 Hz.
Resolution of the DCO using Timer 2 establishes the time jitter of the output frequency relative to the input frequency. Depending on the integer count written to its period register, Timer 2 produces discrete frequencies for output frequency. When the input frequency falls between discrete output frequencies that two adjacent counts produce, the PLL switches between the counts to produce an averaged but jittery outputfrequency signal at the same frequency as the input frequency. Using a relatively large value of N_{0} reduces jitter, whereas a smaller value increases jitter. To improve resolution and reduce jitter, you can increase the clock frequency to 5 MHz by configuring the microprocessor's onchip oscillator to use an external 20MHz crystal.
You can adapt the digital PLL's basic design to a variety of applications by modifying the software and extending the interruptservice routine. For example, stopping updates to Timer 2's period register puts the PLL in "coast" mode. Other expansion possibilities include implementing more sophisticated lockdetection circuitry to determine whether the input frequency falls within a certain frequency range and making dynamic adjustments of the values of N_{0} and K for better performance. Click here to download Listing 1, which is the assemblylanguage source code, as well as the hex programming file for IC_{3}.
Reference 

Simple tester checks Christmastree lights
Move ICs from defects per million to defects per billion
Eye Diagram Basics: Reading and applying eye diagrams
Try an oscilloscope for under $200
RF energy: Measurements improve cooking, lighting, and more
Sensor basics: Types, functions and applications
How to Measure Electrical Power
Please confirm the information below before signing in.
{* #socialRegistrationForm *} {* firstName *} {* lastName *} {* displayName *} {* emailAddress *} {* addressCountry *} {* companyName *} {* ednembJobfunction *} {* jobFunctionOther *} {* ednembIndustry *} {* industryOther *}