Target impedance based solutions for PDN may not provide realistic assessment
Measuring in the time domain offers a large signal measurement solution; however, the method is much more difficult because the ability to control very high-speed current steps is very difficult and might not be possible. This article focuses on the fundamental flaws of using target impedance as an assessment method using simple, lumped element models and simulations to highlight some of the key issues. A high-performance optimization simulator is used to determine the best- and worst-case voltage excursions for a given tolerance.
In a typical high-speed application, a voltage regulator module (VRM) is connected to the load device (often a field-programmable gate array, FPGA, or central processor unit, CPU) through printed circuit board planes and a multitude of decoupling capacitors. The load device itself presents its own parasitic elements, such as the pin and bond inductance and die capacitance. The result of this distribution network is a series of transmission lines, including the printed circuit board parasitic resistance, inductance, and capacitance. In addition, there are multiple decoupling capacitors, which also present parasitic resistance and inductance elements. It is well known that the lowest noise is the result of a flat impedance response over a very broad frequency range. A typical distribution network is shown in Figure 1.
The target impedance at the load is generally defined by the relationship between the allowable noise voltage and the maximum variation in the current demand. A major emphasis is placed on the noise due to this load demand in CPU and FPGA applications because this is generally the largest and most significant noise source.
A typical PDN impedance plot is not necessarily as flat as desired. Even in the lower frequency range, many VRMs and point of load regulators (POLs) exhibit multiple resonances and anti-resonances rather than the desired flat response (see Figure 2).
profiles are flat.
The mathematical evaluation of the voltage noise induced by a change in current can be easily accessed for a second-order distribution network using Laplace and/or Fourier techniques. This simple assessment quickly shows that there are a multitude of possible solutions depending on the nature of the current signal definition and whether the damping of the distribution network anti-resonance is critical, over-damped, or under-damped.
Impact of Current Definition
The Laplace solution of the parallel RLC circuit is easily evaluated as a function of the current through each of the R, L, and C elements.
Which can be rearranged to solve for the noise voltage, V:
In the case that the current signal is a unit step of magnitude ΔI, then the Laplace of the current signal is ΔI/s and the voltage can be written as:
In the under-damped case this results in the solution:
The Q of the parallel RLC circuit is defined as:
Solving for R results in:
Solving for α as a function of Q by substitution:
And finally, we can show that the exponential decay is related to the circuit Q:
If the same circuit is assessed with a sinusoidal current signal at the anti-resonant frequency
, the result takes the form of:
Driving the circuit with a square wave rather than a sine wave results in an amplitude multiplication due to the Fourier coefficient 4/(nπ), causing a 27% larger fundamental amplitude than a sine wave. We have shown that for the under-damped case of a single LCR circuit there are at least three solutions for a constant amplitude envelope, dependent on whether the current signal is a step, sine wave, or square.