Realizing 5G New Radio massive MIMO systems

, & -January 08, 2018

16nm FinFET technology
The monolithic integration of high speed RF components benefits from the excellent analog transistor characteristics that can be wrung out of the 16nm FinFET process. The ON resistance of the transistor is extremely low, which allows implementation of wide bandwidth RF sampling signal switches with high precision. In turn this enables the integration of cost-efficient and power-efficient high speed comparators, amplifiers, clocking circuits, and digitally-assisted analog calibration logic, all with excellent characteristics.

The digital implementation in 16nm FinFET versus 65nm (typically used for analog RF components) results in more than 10× area reduction and 4× power reduction. Xilinx has innovated ideal design solutions to implement power integrity, digital calibration loops for high precision, and robust isolation strategies.

Figure 3 RFSoC digital-RF resources

The digital-RF resources integrated in RFSoC are comprised of multiple channels of 6.4 GSPS DACs and 4 GSPS ADCs, integrated low phase noise PLLs and full complex mixers – 48-bit numerically controlled oscillators (NCO) for each DAC and ADC. The RF data converter arrays come with 1×, 2×, 4×, 8× interpolation and decimation filters and implement flexible FPGA fabric interface. In addition, the direct RF-DAC block implements quadrature modulation correction (QMC) and Sin x/x (Sinc) correction filters.

Massive MIMO in RFSoC
Figure 4 illustrates a typical massive MIMO radio implementation using one of the RFSoC devices. The RFSoC has 33 Gbps transceivers with hardened 100G Ethernet MAC/PCS with an RS-FEC that can be leveraged depending on the flavor of fronthaul interface, be it 25G CPRI or the eCPRI protocol.

Partial L1 functionality, such as iFFT/FFT transforms and associated physical random access channel processing, can be moved to the radio for 50% bandwidth reduction (and cost & power savings) between radio and baseband unit.

RFSoC devices provide rich high performance low power DSP resources to implement a digital front end comprising digital up conversion, crest factor reduction, digital pre-distortion, passive intermodulation correction, equalization, and down conversion.

Appropriate interpolation filters on the transmit path and decimation filters on the receive path are used to run RF-DAC and RF-ADC at high clock frequencies, independent of the FPGA fabric frequencies, for better frequency planning. With careful frequency planning, multiple bands, such as band 1 and band 3 for FDD massive MIMO and band 38, 40, 41 and bands 42 and 43 for TDD massive MIMO, can be simultaneously supported leveraging the wide bandwidth of the integrated RF signal chain.

RFSoC has quad-core ARM Cortex-A53 multiprocessor cores running up to 1.5 GHz along with dual-core real time ARM Cortex-R5 multiprocessor cores running at 533 MHz. This is significant compute resource for computing pre-distortion coefficients and performing system control, RF calibration, and general operation and maintenance functions.

The programmable logic coupled with on chip compute can be used to support open source APIs to future-proof the radio system for software defined networking where radios can be configured dynamically based on the customer demand. Machine learning algorithms can be efficiently implemented in the fabric to automate management of increasing numbers of fragmented spectrum bands, spectrum sharing, and hosting mobile virtual network operators (MVNO).

Figure 4 Massive MIMO radio implementation on RFSoC with partial L1 functionality offload

To enable integration, Xilinx provides a library of state of the art DFE IP for CFR (crest factor reduction) and DPD (digital pre-distortion) along with DFE subsystem reference design and DFE demonstration kits for 4G, LTE-Pro, and 5G applications.

In order to demonstrate system performance on an RFSoC, the ZU28DR device based RFSoC characterization board is connected to a Xilinx RF front end card with two transmit and two multiplexed receive paths to support PA feedback as well (Figure 5). With this board setup, and connecting a single PA to one DAC/ADC pair, a quick port of DFE reference design (v2.1) from an existing Xilinx 16nm MPSoC device was accomplished, leveraging fabric commonality between the RFSoC and 16nm SoC for design reuse.

In this, Xilinx CFR IP was operating at 245.76 MSps (achieving 3% EVM at 7.5dB PAPR with TM3.1a signals) and DPD IP at 491.52 MSps (DAC/ADC operating in 2nd Nyquist using 3.93216 GSps clocks and 8x interpolation/decimation), with a composite signal 2c LTE20 + 1c LTE20 within instantaneous bandwidth of 160 MHz. The PA output is 45 dBm or 32 watts. After running DPD, the achieved ACP (shown on the right side of Figure 5) is 54.91 dBc and upper ACP is −55.14 dBc that complies with sufficient margin for the LTE spectrum emission mask requirements.

Figure 5 RFSoC setup for 2c LTE20 + 1c LTE with IBW of 160MHz

Xilinx All Programmable RFSoCs monolithically integrate high speed wide bandwidth RF-sampling data converters with fabric rich in-digital signal processing and compute resources to address diverse multiband requirements for 5G NR and LTE-Advanced Pro MIMO and massive MIMO radio system implementations. This technology addresses the challenges of massive MIMO by significantly reducing system footprint, power, and cost. The inherent programmability of the RFSoC devices and re-use of existing solutions enables faster time to market while allowing simple field updates to comply with emerging standards and newer algorithms and PA technology.

Paul Newson is a System Architect for wireless communication systems, Hemang Parekh is a Senior Engineering Manager, and Harpinder Matharu is the Director of the Communications Business, all at Xilinx.

Related articles:

Loading comments...

Write a Comment

To comment please Log In