Shift signoff leftwards into physical design: Product how-to
The manufacturing variability inherent in advanced nodes continues to threaten design schedules and design quality. To achieve physical design closure, designs must meet a growing set of complex rules for design (DRC), multi-patterning (MP), and design for manufacturing (DFM).
Figure 1: Increasing DRC and multi-patterning rules
Closing a design for all manufacturing requirements—in addition to traditional performance parameters—is becoming a major bottleneck and results in late-stage surprises and delayed time-to-market.
The traditional physical verification flow of design-then-fix does not work at advanced nodes due to the inherent complexities – new approaches are needed. The assumption that the place and route implementation tool can get “close enough” such that physical verification fixing during signoff is manageable does not hold water anymore. With the introduction of FinFETs and multi-patterning, this assumption begins to break down due to the inherent complexity of the DRC, MP, and DFM rules, and the global nature of the multi-patterning violations. Multi-pattern violations, unlike DRC violations, can impact a significant number of polygons and can span significant distances on the chip.
Clearly, a new approach is needed, one that can detect and eliminate DRC, MP, and DFM issues early during the physical design stage. An integrated design and manufacturing closure solution shifts manufacturing closure work “to the left”, where it is more effective for avoiding late stage surprises and minimizing iterations. An effective manufacturing closure solution must have these basic capabilities:
- Multi-pattern, DRC, and DFM analysis and fixing during design with direct access to sign-off engines to ensure that the manufacturability issues are resolved without introducing new ones or degrading design performance.
- Automatically fix and incrementally verify DRC, MP, and DFM violations at either the block or full-chip level.
- Concurrently optimize the layout for all timing, power, signal integrity (SI), and manufacturing issues.
- Routing technology with native coloring, verification, and conflict resolution engines capable of handling both local and global multi-patterning violations.
Mentor Graphics offers Calibre InRoute (Figure 2), an interactive design and manufacturing closure platform built on Calibre and Mentor’s place and route tools (Nitro-SoC and Olympus-SoC). Calibre InRoute is an add-on to Mentor Place and Route system that enables designers to invoke all the Calibre signoff engines directly during implementation to perform true signoff analysis, and automatic fixing of DRC, MP, and DFM violations. Calibre InRoute provides an API-level interface to both the Calibre and the place and route engines, involves no file transfers, and enables access to the SVRF rule decks during implementation. All violations found with Calibre InRoute are persistent in the place and route database, and can be viewed and edited through the error browser. Calibre InRoute includes the full suite of Calibre capabilities including multi-patterning, DRC, and metal fill.
Figure 2: Calibre InRoute interfaces with Mentor’s place and route systems, Nitro-SoC and Olympus-SoC.
Consider a standard place and route flow. The tool avoids as many DRC and DFM violations as possible during initial routing, then calls it’s native DRC and DFM checkers and finds the design to be free of DRC violations. However, when the design is analyzed with Calibre, nearly 1500 violations of a complex end-of-line rule caused by incorrect spacing from the adjacent via pad are uncovered.
Figure 3: End-of-line rule violation found only during signoff verification
Using the traditional methodology, you annotate the violations to a layout editing environment and fix them manually, then run new timing, signal integrity, and power analyses and another signoff check. But, fixed items might introduce new violations that require additional iterations through the fix-then-verify loop. The changes also have unintended impacts on a critical clock path, so although within spec, the overall design is no longer fully optimized.
In contrast, if you perform signoff within place and route using Calibre InRoute, you would load the Calibre SVRF deck, choose the rules that need to be validated, and execute signoff analysis by adding one option, -mode calibre, to the standard check_drc command in the router. The SVRF-based analysis reveals the same 1500 violation instances in the end-of-line rule as found in the stand-alone Calibre run, but now the router automatically fixes them while running the Calibre sign-off engine.
Figure 4: Calibre InRoute provides an integrated design and verification environment with automatic fixing to enable designers to close manufacturing issues while they are creating the layout.
After repair, the fixes are Calibre-clean by definition. For the end-of-line issue in this example, Figure 5 shows the before and after layouts, indicating how Mentor’s place and route rerouted the wire to fix a violation using information from Calibre. Using Calibre InRoute significantly speeds up the manufacturing signoff process compared to the traditional signoff verification followed by manual fixing, stream out and re-verification.
Figure 5: Before and after layouts, showing how Mentor’s place and route has rerouted the layout to fix a violation using information from Calibre.
Shifting physical verification signoff into place and route minimizes the gap between design and signoff environments to improve design schedules and design quality and speed time-to-market. With Mentor’s Calibre InRoute, manufacturing closure that traditionally takes weeks or months can be reduced to days.
—Arvind Narayanan is a Product Marketing Manager at Mentor. He holds a Masters in EE from Mississippi State University and a Masters in Business Administration from Duke University.