Ternary DAC: Greater resolution, less bits

-October 02, 2017

I was delighted when reader and DI contributor Jim Brannan proposed writing up his base-3 DAC design. Like Charlieplexing, his idea makes use of tristate outputs to wring more information from a pin than just “0” & “1”! A four-“bit” DAC, for example, is theoretically able to generate 34 (81) levels instead of the usual 16. Five bits would essentially match regular eight-bit performance (243 levels), though presumably accurate implementation will be more difficult than a regular binary DAC, especially as resolution increases.

As usual, I Googled around to check for prior art, and yup, found two pages describing similar beasts. Jim had a look, and decided he didn’t have anything to add, so…no Design Idea. But I felt the concept was worthy of some publicity anyway. And Jim did have his own unique approach too.

Before continuing, perhaps take a moment to imagine how you might implement a ternary DAC. Maybe you’ll come up with a new variant, before straightjacketing your mind with the ideas below.

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Okay, here’s my own implementation idea:



Figure 1
  Summing amp with mid-supply reference implements a base-3 DAC.

Actually, my initial idea had the amp’s (+) input at -VDD, but I then realized that a floating output would be pulled towards that negative supply, probably clamp at -0.7V, and generally not work. The VDD/2 reference means 0,1,2 states correspond to 0,Z,1 outputs (“Z” means high-impedance and/or input mode).

Another hardware concern is that some microcontrollers may draw excess supply current when inputs are at mid-rail, so verify that's not a problem, disable digital-input mode, or use pins that can be set as analog inputs.

Driving a ternary DAC will require either a lookup table or a binary to ternary conversion routine. In most cases, the DAC output will glitch when its setting is changed, unless pin mode & value can be set in one write cycle.

Jim’s aborted Design Idea uses a passive “R-2R” style DAC, and he wrote software to search through many resistor combinations. Unable to create a perfectly linear DAC, his solution is to use a lookup table and live with somewhat uneven performance.

On his blog, Josh Bowman describes his own take on a base-3 DAC. The structure is R-2R-ish, with lower value resistors dividing the supply to generate the mid-level ‘Z’ values.


Figure 2  Josh Bowman’s passive ternary DAC


As you can see below, there are redundant values in the design, which enables calibration.
 


Figure 3 
Raw and calibrated INL performance


 
A couple of base-3 DAC designs, variations on those above, are also discussed on this Arduino forum.

Recount your experiences below if you attempt a ternary DAC implementation. We’d love to hear about it. And remember, as with all such simple DAC designs, power supply noise will feed through to the output.
 
Also see:

 
Michael Dunn is Editor in Chief at EDN with several decades of electronic design experience in various areas.

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