How to prevent capacitor failures

Brad Brim, Cadence Design Systems -January 07, 2016

Have you ever owned audio equipment or other electronic products that quit working after several years? Have you ever had one of your designs return from manufacturing test or customer usage due to power delivery issues? Many such failures are due to failure of capacitors in the power delivery network (PDN). It is well known capacitor behavior varies with bias voltage, temperature and product age. If you wish for the electronic products you buy and design to operate properly they should be designed with consideration for these unavoidable effects. Component manufacturers should understand and document these effects for designers and EDA tools should readily apply them in simulations.

At this year’s DesignCon, we will be addressing these issues in the panel Needs and Capabilities for Modeling of Capacitor Derating on Wednesday, January 20 from 3:45pm – 5:00pm in Ballroom D at the Santa Clara Convention Center. This panel session will summarize an ongoing discussion among a small group of OEMs, component vendors and EDA vendors and seek audience feedback to represent industry guidance for how such effort should proceed. The discussion concerns component modeling requirements for consideration of effects such as bias voltage, instance temperature, and finished product age. Discussion initiated with the objective to support greater generality and automation for simulation of PDNs. These effects often cause changes in the capacitance of PDN decaps; a phenomenon commonly referred to as “derating.” The title of the panel session reflects this initial objective, though a robust solution to the present needs will also support other component types for many different applications.

I will moderate the session with a brief introduction to the topic. Panelists will then briefly present their views on the challenges and potential solutions. Then we will do questions and answers. Istvan Novak (Oracle) and Tim Michalka (Qualcomm) will represent OEM needs for generality and automation of electrical analysis for a diversity of high-speed designs. Wilmer Companioni (Kemet) and Shoji Tsubota (Murata) will then present component modeling issues and potential future contributions with consideration of technical challenges and customer needs. Sam Chitwood (Cadence) will follow with a discussion of how simulations may include more general physical effects and greater analysis automation. All presentation and back-up material slides will be available to attendees.

Audience participation is key for guiding an initial industry approach to the challenges of considering component electrical performance dependence on effects such as bias, temperature and age. If you cannot join us in the discussion on site at DesignCon, please post your questions below.

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Want to learn more? Attend DesignCon 2016, the premier conference for chip, board, and systems design engineers. Taking place January 19-21, 2016, at the Santa Clara Convention Center, DesignCon will feature technical paper sessions, tutorials, industry panels, product demos, and exhibits. Register here.
DesignCon and EDN are owned by UBM.

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