Target impedance, rogue waves: tales from the experts
If you care about power integrity, you do not want to miss this all-star panel of PDN experts offered on the last day, at the last session of DesignCon 2016. On Thursday, Jan 21 in Ballroom GH at 3:45, we will gather in one place a significant fraction of the industry’s power integrity brain trust. From Oracle, is Istvan Novak. From Qualcomm is Larry Smith. From Picotest is Steve Sandler, and from Cadence is Brad Brim.
I have the distinct honor, and challenge, to moderate this panel. Collected at this one table will be more than 100 engineer-years of expertise in power integrity and successful PDN design. These are some of the most influential leaders in PDN design. Many of the other papers in the technical sessions you will hear at this DesignCon are based on the pioneering work these icons of the industry presented at DesignCon over the last ten years.
Does it really matter what they’re going to talk about?
Just so you know, the specific focus of this panel is target impedance and rogue waves. Last year, Steve Sandler “rocked” his PDN tutorial audience with the observation that a rogue wave in the PDN can really ruin your day. He made the challenging comment that “designing for a target impedance may not be the right approach, as it can’t protect you from rogue waves.”
A rogue wave in the ocean occurs when many smaller amplitude waves, each with different frequencies, are driven with just the right phase coherence for their amplitudes to superimpose in the worst possible way. Rogue waves, while rare, have been known to sink ships. Even if they are rare, if they can kill, don’t you want to know how to avoid them?
Our panel of industry experts will re-examine this question. Are rogue waves in the PDN a white whale that can sink your PDN design or a red herring you can use for bait? Join us for what will be a lively discussion, and bring your questions for this world-class collection of experts.
- Two common PDN measurement questions
- Design a VRM with perfectly flat output impedance in 5 seconds or less
- Make sense of high-frequency test methods
- Profiles in Design: Brad Brim
- Profiles in Test: Steve Sandler
- Profiles in Design: Istvan Novak
- Profiles in Design: Eric Bogatin
Want to learn more? Attend DesignCon 2016, the premier conference for chip, board, and systems design engineers. Taking place January 19-21, 2016, at the Santa Clara Convention Center, DesignCon will feature technical paper sessions, tutorials, industry panels, product demos, and exhibits. Register here.
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