DesignCon2016: Prepare for the PAM4 phase shift

-December 04, 2015

If you want to take the temperature of the state of electronics design, don't miss DesignCon's traditional opening night panel.

It’s going to be different this time.

2016 will be 14th year that The Jitter Panel (well, the official title filtered through our marketing department is The Case of the Closing Eye) hosted by Chris Loberg and executed (or perhaps immoderated) by yours truly, will kick off the annual familEE reunion that we call DesignCon. The panel puts test and measurement gurus face-to-face with problems from their most challenging customers. The difference is that, this time, the T&M people don't have their pre-planned bill of goods for sale—not a lot of new automated tests, crazier acronyms, higher bandwidths, contradictory product names—no, this time they're more like confused 7th graders at the school dance. They want to dance, but they don't know how to attract the ASIC and FPGA designers onto the floor.

You probably felt the wind shift as line rates surpassed 25 Gbit/s and PAM4 (4-level pulse amplitude modulation) pushed aside the simple, intuitive high/low, 1/0 baseband digital signals that we used to call NRZ (non-return to zero) but will soon be calling PAM2 (it is, after all, 2-level pulse amplitude modulation). Seems like yesterday that we could look at a signal and read logic levels from waveforms, but the truth is that ISI (inter-symbol interference) has been eating our lunch for years.

We staved off ISI's assault with clever clock recovery schemes, de-emphasis at the transmitter, and CTLE (continuous time linear equalization) and DFE (decision feedback equalization) at the receiver. No one can say we didn’t push good old NRZ (a.k.a., PAM2) to its limit.

Don't worry, PAM4 is here to help. By coding two bits per symbol, PAM4 transmits twice as much data as PAM2-NRZ at the same symbol rate. This figure indicates the added complexity of PAM4 signaling compared to PAM2.

Comparison of PAM4 and PAM2 signals shows what's in store. (Courtesy of Tektronix)

Sixteen different bit transitions compared to four. Six rising/falling edges compared to two. And, check out the eye diagram: it's like the iris of a mutated goat.

A PAM4 eye diagram is certainly more daunting than a PAM2-NRZ eye. (Courtesy of Tektronix)

While a goat's eye resembles a PAM4 eye, the goat is perfectly  happy with just two eyes as where PAM4 needs three.

With three eyes packed into the same peak-to-peak voltage swing where we've been struggling with one, PAM4 is about three times more signal-to-noise challenged than PAM2-NRZ. Some of the issues are obvious: one symbol error can mean two bit errors, crosstalk is three times more likely to cause errors, and the relative timing and voltage widths (i.e., eye height) of each eye can differ.

The designers have a year under their belts and are still discovering the obscure issues that will challenge PAM4 designs:

Can DFE get us over the hump?
Will DFE plug and play into PAM4 with just a few taps bringing BER salvation? Or will having four separate decisions to feed back require greater sophistication to open our signal-to-noise suffering eyes? But each tap sucks more power, and there’s the avalanche problem, too…

How far can FEC (forward error correction) take us and at what cost?
To address PAM4's signal-to-noise problem, FEC has been included in the specifications so that the data-link-layer can achieve BER better than 1E-12 (or, the optimists say, 1E-15) even as the bare physical layer sits around 1E-6.

A year ago, it seemed like Reed-Solomon FEC (forward error correction) could handle the propensity for (decision feedback equalization) to cause avalanche errors, but now we’re starting to see signs that the avalanches might be too long for FEC to recover. Plus, correcting the errors takes time and the latency might be more than some applications can afford.

Can analog decision circuits deliver the required BER or will the power budget be broken by ADCs?
With three logic levels, ADCs (analog-to-digital convertors) will replace simple voltage slicers, improving sensitivity from around 30 mV to 5-10 mV but at a cost of two to three times more power.

Will COM (channel operating margin) continue to horrify children and send test engineers to the loony bin?
COM is famous for lumping all signal impairments into one handy TLA that’s easy to transport from one modulation scheme to another because hardly anyone understands it, almost no one can calculate it, and the only person who could measure it gave up EE to become a yoga instructor.*

So far, I haven't come across anyone who's suffering too much from PAM4 eye-compression—the nonlinear variations in the vertical opening of the three eyes—at least, not on in electrical applications, but optical applications of PAM4 will catch up with electrical and that bubble might pop.

To ponder these questions, join DesignCon's signal integrity clerics as they burning incense, meditate on COM, read tea leaves, and apply the dual Dirac model to eye diagrams that have three pupils.

But wait, for DesignCon 2016 will have a second PAM4 panel, PAM4: New measurements are coming, which closes out DesignCon 2016 on Thursday, January 21 at 3:45 pm.

* My source for COMments has a propensity for exaggeration.

Want to learn more? Attend DesignCon 2016, the premier conference for chip, board, and systems design engineers. Taking place January 19-21, 2016, at the Santa Clara Convention Center, DesignCon will feature technical paper sessions, tutorials, industry panels, product demos, and exhibits. Register here.
DesignCon and EDN are owned by UBM Canon.

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