Is your spacecraft flying reliable chips?

-February 25, 2014

The space industry wants to exploit the higher integration, faster processing and lower power consumption advantages of ultra-deep-submicron microelectronics. As the number and capability of dedicated radiation-hardened foundries has dropped compared to commercial fabs, designers of space-grade integrated circuits have switched to consumer-grade, semiconductor technologies to meet their on-board processing needs. A number of current developments are baselining 65- and 45-nm nodes.

Commercial semiconductor processes are typically optimised for yielding circuits with high density, speed and low power consumption for consumer applications within a terrestrial environment, e.g. a lifetime between five to ten years and an operating temperature range from 0 to +80°C. Satellites require electronics to function over a military temperature range from –55 to +125°C, and since most ultra-deep-submicron failure modes are thermally activated, there is no guarantee that reliability at +80°C will be applicable at +125°C. For hot-carrier effects, lifetime degrades as temperature is lowered and there is no assurance that reliability at 0°C will also be valid down at -55°C.

Unlike dedicated radiation-hardened foundries, commercial fabs will not deliver qualified QML or ESCC components as defined in MIL-PRF-38535 or ECSS 2269000 respectively. The onus now resides with the semiconductor supplier, who has become responsible for process and package qualification, as well as irradiating, testing and qualifying lots for delivery to the end customer.

In general, CMOS scaling has improved the total-dose and latch-up sensitivity of space-grade microelectronics. Thinner gate oxides trap less positive charge while lower supply voltages and the reduced gain of the parasitic, bipolar, silicon-controlled rectifier bolster total-dose and latch-up immunity respectively. Single-event effect (SEE) mitigation has become more challenging as increased circuit densities require less overall charge to disrupt sensitive locations.

However, Moore's law has progressed faster than proportional reductions in the level of the supply voltages, with each generation producing increased electric fields within the gate dielectrics of MOSFETs. This has exacerbated the reliability problems associated with ultra-deep-submicron processes as the larger electric fields are a source of damage to materials and interfaces.

To meet the relentless integration, processing and power consumption demands of the consumer electronics industry, foundries are continually offering innovative solutions to improve transistor performance, e.g. high-K dielectrics, metal-gate materials, silicon straining layers, low-K interlayer dielectrics, new metallization concentrations, multi-threshold transistors, triple-gate oxides, variable gate-length transistors and copper routing.

The implications of the above innovations on radiation hardness and mission reliability are not yet fully understood and characterisation and analysis of technologies is needed to assess their suitability for fifteen to eighteen year space missions at elevated junction temperatures. Research presented in the last two to three years suggests that total-ionizing dose and heavy-ions exacerbate the intrinsic failure mechanisms of ultra-deep-submicron microelectronics.

For ultra-deep-submicron microelectronics, the key reliability concerns comprise effects that degrade transistor performance or cause circuit malfunction before the specified operational lifetime. The failure mechanisms are typically accelerated by increased operating voltage and temperature and include material, stress, mechanical and environmentally-induced effects. Some intrinsic, integrated-circuit, failure mechanisms are listed below:

Time Dependent Dielectric Breakdown (TDDB) occurs when the cumulative effect of trapped charge in the oxides increases device noise, gate leakage and, in the extreme, dielectric breakdown. The gate oxide of a MOSFET needs to have a very high resistance to source, drain and channel. However, after some period of time with continued electric field stress on the gate oxide, TDDB causes a decrease in resistivity and a significant current can be conducted across the insulating oxide. The physical realisation and size of transistors can be used to improve TDDB reliability.

Hot Carrier Injection (HCI) occurs when carriers near the drain edge of a MOSFET gain sufficient momentum to overcome the energy barrier between the silicon and silicon dioxide gate, and are injected into either the gate oxide or the dielectric near the edge of the gate. HCI causes the charge carriers to become trapped permanently changing the switching characteristics of the transistor. Electrical and design rules can be used to minimise the time a cell spends at conditions of maximum substrate current, e.g. lowering the supply voltage, reducing the clock frequency, increasing the channel length, optimising the load capacitance and the use of edgeless, annular transistors.

Negative Bias Temperature Instability (NBTI) occurs primarily in PMOS FETs due to trapped charge in the gate oxide interface traps at high voltage and elevated temperature. NBTI results in threshold voltage increases and degraded drive trans-conductance.

Electromigration (EM) occurs when excessive current densities in conductors form small voids, increasing bulk resistance ultimately leading to conductor burn-out. With continued CMOS miniaturization, the probability of failure increases because both power and current density increase. Limiting the maximum allowed densities within designs can increase lifetime. The following photographs show EM-induced voids in the sidewall of a via.

I've only just skimmed the surface on the use of ultra-deep-submicron microelectronics for space applications and long-term SEE and reliability concerns. With qualified, 65-nm, standard products now in-orbit and other developments in progress, process and foundry selection must consider failure and aging mechanisms to ensure the latest semiconductors do not wear out before the end of a mission.

Last month, ESA's Rosetta spacecraft woke from its thirty-one month slumber. Rosetta was originally launched in 2004 and will reach the Churyumov-Gerasimenko comet later this year. Imagine if its microelectronics had worn out in the time between lift-off and before the 'real' science begins. Telecommunication operators are asking for satellites to function in-orbit for longer and the latest digital channelizing payloads mandate the use of ultra-deep-submicron nodes to deliver the requested on-board performance.

I'd like to hear about your ultra-deep-submicron design experiences for space applications, particularly if you have any interesting radiation-hardening-by-design or reliability experiences to share. In addition to device and application considerations, technology selection places even more emphasis on long-term reliability and the willingness of commercial foundries to offer suitable process monitors and stress data to the space industry.

I've been asked to publicise two conferences that will take place later this year: ESA's International Workshop on Analogue and Mixed-Signal Integrated Circuits, which will take place at CERN in Geneva, Switzerland this June, and a joint NASA/ESA Conference on Adaptive Hardware & Systems which will be held in Leicester, UK this July. Please contact the relevant people at either event if you wish to present or attend - it would be great to see some papers on techniques that can be used to monitor and adapt to intrinsic transistor changes that affect performance during the lifetime of a mission.

P.S. In case you are thinking of moving house, check-out this video of a potential new home:

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