Introducing the world’s first 28nm semiconductor for space
The specification of the 5SGXMA7H2F35C2, its range of logic resources and innovative fabric design, exceeds by several generations the speed, bandwidth, and power advantages of current space-grade ASIC technology. For the first time, space users will be able to avail of ultra-deep-submicron performance without having to pay large, up-front NRE costs.
The specification of the 5SGXMA7H2F35C2 will allow operators to offer many new types of satellite services enabling tomorrow's space-based economy. Its 14.1 Gbps serial links will directly interface to the next generation of high-speed JESD204B ADCs/DACs offering larger instantaneous bandwidths and greater throughputs of data. This capability will enable more recent applications for space such as VPX, RapidIO, SpaceFibre, and improved TT&C. The FPGA offers 622k logic elements, 939k registers, 50 Mb of internal storage, and sub-GHz I/O speeds.
The 5SGXMA7H2F35C2 will enable the next generation of missions for the space industry, supporting the development of large- and small-satellite technology, payloads, platforms, spacecraft avionics, launchers, and scientific instruments.
Unlike other FPGAs, which are developed for high-speed operation only, the fabric of the 5SGXMA7H2F35C2 is optimised for low-power operation. Only the small percentage of actual timing-critical logic is assigned to faster transistors and the design software, Quartus 2, automatically selects between high performance or low power transistors on a per-tile basis. At a process level, this is achieved by varying the back-bias voltage of the internal FETs which in turn changes their threshold voltage as illustrated below.
The ability to optimize performance together with power consumption means the 5SGXMA7H2F35C2 can be re-used as a common architecture within all payload and platform sub-systems, e.g. for less processing-intensive applications within a spacecraft such as localized control of a power supply, a transistor or ferrite driver, and TT&C. This will allow OEMs to have a single design for all on-board processing, minimizing NRE and RE effort and costs and the bill-of-materials, ensuring your products get to market faster--right-first-time!
The same die will be used in both 1152-pin, 1 mm pitch, flip-chip options: the screened, commercial, metal-packaged device and the QMLY, ceramic version to satisfy the reliability needs of different customers. These are pin-to-pin compatible, requiring a single layout for prototyping, qualification, and the final flight design, minimizing NRE, hardware-development effort and costs. Furthermore, the FPGA performance between the different quality grades is fully representative, making timing closure easier to achieve from proof-of-concept to flight.
Compared to current space-grade FPGAs, the 5SGXMA7H2F35C2 offers the highest levels of performance in terms of bandwidth and processing throughput, the most extensive range of logic resources, low static, and dynamic power consumption, fully-representative prototyping, intrinsic total-dose and latch-up immunity, robust SEE mitigation of configuration and user memories, SEU fault injection and a SEFI characterization capability to achieve the lowest, soft-error rates for the highest-reliability missions.
Continued CMOS scaling has resulted in lower core voltages that have dramatically reduced the dynamic power consumption of commercial, ultra deep-submicron FPGAs. Advances by Altera at the process level, as well as architectural innovations within the fabric, have prevented corresponding increases in static power. The 5SGXMA7H2F35C2 requires a core voltage of 0.85V, which has significantly lowered dissipation (α V2) as well as leakage currents (α V3).
Altera offers a Reliability Report, which includes the FIT rates from accelerated, high-temperature, and high-voltage life tests, humidity (HAST/THB) data, and MTTFs for solder-joint integrity as well as shock and vibration.
For customers who have signed an NDA, a Process Qualification Report describing the reliability of the 28 nm fabrication technology is available. This includes lifetime and semiconductor wear-out data. To support future customers, a Space-Systems Handbook can also be requested which introduces the architecture of satellite and spacecraft sub-systems, includes a primer on the space environment, semiconductor radiation effects, and more detail about the fabric, capability, and reliability of the 5SGXMA7H2F35C2.
Ultra-deep-submicron fabrication intrinsically offers higher, total-dose immunity as thinner oxides trap less positive charge, as well as better SEL tolerance, due to advances in processing and the fact that power-supply rails have become smaller than the latch-up, holding voltage. SEL and SEU testing is currently taking place using a custom, radiation-testing platform with results to be released in the coming months.
Altera is creating a new user community for the space industry with members receiving discounted development kits, free IP and source code, and the ability to borrow boards and tools to support your next product.
I have just completed my first hardware design baselining the 5SGXMA7H2F35C2 and throughout 2015 and 2016, I will be posting a series of tutorials specifically for the space-electronics community.
The next article will introduce the 5SGXMA7H2F35C2 FPGA's design software, known as Quartus 2, including a video demonstrating the design flow and how to implement a VHDL example used by the space community.
The third article in the series will demonstrate the SEE mitigation features available within the 5SGXMA7H2F35C2, including protection of the configuration and user memories, SEU fault injection and SEFI characterization.
The fourth article will demonstrate the 8 to 14.1 Gbps, high-speed serial links offered by the 5SGXMA7H2F35C2, with an example correlating the bit-error rate predicted by Altera's Transceiver Toolkit and EyeQ software with actual, board-level measurements.
Further articles will describe how to design the 5SGXMA7H2F35C2 into your next space product, comparing the implementation of algorithms and discussing hardware and software development, e.g. benefits of dynamic on-chip termination, hard (non-configurable) vs. soft-IP for space applications, power-estimation and power-distribution spreadsheets, system debug, and IBIS-AMI simulation using Linesim from Mentor Graphics and Altera's JNEye link-modelling software.
The announcement of the 5SGXMA7H2F35C2 COTS FPGA for space begs the obvious question: why consider 90 or 65 nm space-grade ASICs with their large NRE expense for your next product, when you can have full re-programmability, lower power consumption, and the blistering performance of a 28nm FPGA at low cost?
If you have any questions about designing-in the 5SGXMA7H2F35C2 into your next space product, you can contact me here or via my Linked-In group, Out-of-this-World FPGAs.
Altera will be exhibiting at DSEI in London this September where space customers can discuss their future on-board digital-processing requirements by contacting Ching Hu.
Until next month, download Quartus 2 and let’s enable your next generation of space products!