Cars drive new DFT technologies

-March 04, 2014

Automotive electronics is among the faster-growing segments of the semiconductor industry, and the standards for these safety-critical devices are driving the new DFT (design-for-test) technologies. Not since the invention of embedded compression have I seen such important advances in test. With those advances in test comes the need to design for test.

Design-for-test has sometimes been the forgotten stepchild of IC design. But the new demands of devices used in safety critical applications—automotive ICs in particular—are driving resurgence in DFT technologies. We live in an exciting time to be in test! The number of processors within each car is steadily increasing. These processors are used for breaking systems, engine control, heads-up display, navigation systems, image sensors, and more. It's a hot business, but not an easy one. Chips have to meet very high standards for quality and reliability, so the companies who make them need high-quality manufacturing test as well as in-system test. Not only that, but manufacturers must perform better tests without increasing test time or cost.

We've seen two test methods being rapidly adopted by many companies that are developing safety critical devices. One is Cell-Aware ATPG, and the other is hybrid ATPG/LBIST. Cell-aware supports a zero DPM (defects per million) goal. Hybrid test improves quality and efficiency by combining ATPG and LBIST logic circuitry.

Cell-Aware ATPG can detect defects that escape traditional tests. It can find defects that would escape a 100% stuck-at, transition, and timing-aware test sets because it starts by modeling the actual defects that can occur in the physical layout of standard cells. Cell-Aware pattern size was recently improved and reduced, but a complete pattern set is larger than a traditional pattern set so embedded compression is used. Many companies are having success with Cell-Aware test. Some results are summarized in Figure 1.

Figure 1. Silicon results from companies using Cell-Aware test as of December 2013. The On Semiconductor results were published at ETS 2013, and the AMD results were published at ITS 2012.

At Mentor Graphics, we've seen more and more customers using both embedded compression and logic BIST (built-in self test) for the same circuits. This gave us the opportunity to make this approach more efficient for our customers by integrating both into common logic that can be shared, since both technologies interface to scan chains in a similar manner. The architecture of our hybrid test logic is shown in Figure 2.

Figure 2. The logic architecture of a hybrid compression and logic BIST shares a majority of the decompressor/LFSR and compactor/MSIR logic.

The embedded compression decompressor is designed to also be configured into a LFSR (linear feedback shift register) to produce pseudo-random patterns for logic BIST. Both the logic BIST and embedded compression logic provide data to scan chains through a phase shifter so that logic is fully shared. The scan chain outputs are compacted together in embedded compression. This logic is mostly shared with logic BIST to reduce the number of scan chain outputs that enter a signature calculator. The shared logic saves 20-30% on the controller size over implementing embedded compression and logic BIST separately.

A bonus of using embedded compression and logic BIST together is that each makes the other better. For example, embedded compression gives extremely high-quality production test. This means you need fewer logic BIST test points to make random pattern-resistant logic more testable, which reduces the area of logic BIST test points. Conversely, the X-bounding and any test points that are added for logic BIST make the circuit more testable and improve the embedded compression coverage and pattern count results.

Also see
Cell-aware ATPG test methods improve test quality Address FinFET test challenges
How to generate test patterns to detect FinFET defects
Ensure FinFET defect coverage with cell-aware test

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