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10.22.98  Design Idea

-October 22, 1998

 


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October 22, 1998

Ethernet 10BaseT simulator jig yields zero emissionsGlen Chenier, Fujitsu Network Communications, Richardson, TX
A test jig (Figure 1) is a valuable tool because it evaluates RF emissions from Ethernet unshielded-twisted-pair (UTP) 10BaseT LAN-interface devices without contaminating the measured results with its own RF emissions. When an RF-emissions-measurement lab tests a multiport, UTP 10BaseT Ethernet device for compliance with FCC-radiated emission limits, the test is meaningful only if the device transmits data packets from all 10BaseT ports. To enable this transmission, the 10BaseT ports must receive a steady stream of link test pulses from attached 10BaseT devices. Unfortunately, the attached devices commonly radiate from their attached cables on the same frequencies as the equipment under test (EUT). This problem makes EUT performance evaluation and any trial fixes difficult, if not impossible. The solution is to eliminate the radiated noise from the ancillary equipment.
 
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A test generator outside the measurement area can avoid interfering emissions from the generator and its cables by generating the packet data and feeding it over optical fiber to an EUT port. But the EUT 10BaseT ports still need a source of link test pulses to retransmit the data packets. To evaluate EUT emissions from the cables, these sources must connect to the EUT by UTP cables of at least 1m. Only emission-free link-test-pulse sources provide an accurate evaluation of the EUT. The emission-free requirement is difficult to meet when the link-test-pulse sources are 10BaseT devices with noisy 20-MHz clock oscillators and digital circuitry.

The circuit in Figure 1 generates the required link-test pulses without RF emissions. The pulse must have a width of 60 to 130 nsec with a repetition frequency of 42 to 125 Hz. Pulse amplitude should be 500 mV to 3V. This test jig outputs pulses of about 1V, but you can easily change this level by changing the value of R2.

For convenience, the jig operates from a 9V battery. The use of CMOS devices results in a current drain of less than 100 µA. According to battery specifications, this current drain translates to an expected battery life of several thousand hours. The duty cycle of the link test pulses is 100 nsec/20 msec=0.0005%, so little battery energy is necessary to drive the EUT receivers. A pushbutton battery-test feature using zener diodes and a four-LED bar-graph display ensures that the battery is capable of the day's testing. To extend battery life, a pushbutton EUT-monitor circuit verifies that the EUT is working properly and is actually transmitting data packets from each port you test.

The frequency of the master oscillator (IC1) is 50 Hz, which spaces the link-test pulses at 20-msec intervals. This low frequency has low harmonic energy in the 30-MHz and higher portion of the RF spectrum; thus, it achieves the primary design goal. IC1, a micropower LPC661, has low power consumption, yet its slew rate is fast enough that the input of the following 74HC132 Schmitt trigger stage (IC2A) is between the rails for a minimum time.

You can eliminate IC1 and use IC2A as the oscillator, but the power consumptions of HCMOS gates and Schmitt triggers tend to rise drastically when the input voltages are not at supply rails. A Schmitt-trigger CMOS oscillator has a constant sawtooth centered linearly between its trip points at its input. The measured difference in the jig's total power drain is 6.5 mA with the HCMOS oscillator and 85 µA with the LPC661 oscillator. Long battery life is a secondary design goal.

The pulse generator uses a 100-nsec RC-delay line (R1, C1), and a Schmitt-trigger buffer (IC2B) to present the 50-Hz square wave and a 100-nsec delayed version of this square wave to the inputs of NAND gate IC2C. Thus, IC2C's output consists of 100-nsec-wide pulses at 20-msec intervals. The pulse-driver gate (IC3) inverts these pulses to drive the output transformer through a 390 Ohm current-limiting resistor (R2). The transformer is a 1-to-1 Ethernet transformer. You can use other types of transformers with built-in filters; however, the low pulse-repetition rate does not require a bandlimiting filter. Changing the value of R2 varies the nominally 1V output's amplitude.

Two RJ45 jacks connect the simulator to the EUT. The test jig includes both normal and crossover-wired jacks so that you always have the jack you need for the available UTP cable.

The EUT-monitor circuit includes the 100 Ohm termination (R3) for the EUT-transmit pair. Keep the leads in this area short and symmetrical to avoid reradiating the data packets from the EUT and causing false emission readings. Even with VCC off, IC4 has a high input impedance to avoid generating and reradiating harmonics of the data packets. When you depress the EUT-monitor test button, any input data activity causes the IC4's output to toggle at the packet data rate. The negative-going data pulses discharge C2, resulting in a high output from IC5's Schmitt-trigger inverter, which in turn lights the LED.

R5, a 200 Ohm resistor, slows the capacitor's discharge time constant enough to ensure that any overshoot or ringing from the EUT's positive-going, individual link test pulses do not light the LED. Only actual data packets have a pulse density sufficient to light the LED. Once discharged, the low-leakage diode, D1, and the 1M R4 increase the capacitor's recharge time (the period after the end of the packet when IC4's output is high again). The lengthy recharge time extends the LED's on-time to 100 msec for maximum visibility.

You can add any number of pulse-driver and EUT-monitor sections to the basic circuit, depending on the number of simulator ports and the limits of the LM2936 regulator when all LEDs are on. If you wish to power the EUT-monitor circuit from a separate higher power regulator, place the pushbutton at the additional regulator input so that the regulator's quiescent-current drain does not unnecessarily load the battery. If you don't wish to incorporate the EUT-monitor circuit, you still need to place the 100 Ohm termination resistor across the EUT-transmit pair, but you will no longer need the input transformer. (DI #2235)

Digital potentiometer autonulls op ampStephen Woodward, University Of North Carolina, Chapel Hill, NC
Op-amp applications that need the highest possible dc accuracy are generally best served by CMOS chopper-stabilized amplifiers, such as the LTC1050. But high-speed, low-noise applications may require high-performance rockets, such as the 700-MHz LT1226. So what to do for applications that need it all? Sometimes, a composite topology in which a bipolar amplifier provides gain-bandwidth and a CMOS chopper acts as an offset-nulling servo can do the job. Such arrangements can successfully null out offset-voltage errors. But these circuits can get messy if you also need bias-current-related error correction. The circuit in Figure 1 offers an error-cancellation method that handles both error sources.

The circuit consists of op amp IC1 (for example, Linear Technology's LT1226), CMOS multiplexer SC (one-third of an HC4053), and digital potentiometer P1 (Xicor's X9C103). The topology supports two modes of operation, as selected by the TTL/CMOS-compatible NADJ signal. NADJ=0 connects IC1 as a standard noninverting gain block. The circuit values shown, combined with the impressive specs of the frequency-compensated LT1226, provide a gain of 1001 with bandwidth extending from dc to beyond 500 kHz and input-related noise of approximately 2 nV=Hz.

Null-adjustment mode occurs when NADJ=1 disconnects the input source and effectively causes IC1's output to run open-loop. IC1's output and then slews to one rail or the other, as determined by the sign of its net offset error. If R3=RS-R1||R2, where RS is the dc source resistance, then IC1's output reflects the sum of both voltage and current bias errors. The circuit level-shifts and filters IC1's output and applies it to the up/down control input of P1. This action sets up P1's internal up/down-counter logic to increment or decrement one step, depending on the state of IC1's output and thus on the sign of IC1's offset. The counter step occurs on the subsequent NADJ=0 transition.

The connection of the VL,VW, and VH terminals of P1 to the nulling terminals of IC1 closes a feedback loop that tends to push IC1 one step toward null for every I/O cycle of NADJ. Because the X9C103 has 100 resolved settings, the technique requires a maximum of 99 NADJ pulses to complete the nulling process. After nulling, P1 retains the final null setting in digital memory as long as the 5V supply remains connected or until the nulling process repeats. Observed performance reveals that using an OP37 consistently achieves residual-offset errors of less than 5 mV.

If it is inconvenient to provide an external NADJ clock source in a given application, you can add the SA/SB multivibrator at Node 1. This 1-kHz clock circuit receives its gating from the CMOS-compatible anull signal, such that anull=1 enables continuous null adjustment, and anull=0 enables normal amplifier operation. The maximum anull duration required to achieve initial null is 100 msec. If desired, you can also include D1, R8, and C3 at Node 2 to provide an automatic null on each power-up cycle.

Although Figure 1 shows an LT1226, the circuit works without modification with an OP37 and an LT1028. The circuit is also pin-compatible with the popular LT1128, OP07, OP77, OP177, and m725 op amps. With these op amps, however, the circuit may require a slower NADJ clock rate and a longer nulling interval (increase C2 and C3), because of the lower gain-bandwidth product of these compensated types. The circuit can accommodate many other op-amp types with a simple change of pin connections. The circuit can handle 15V positive-rail operations by substituting an X9312 for the X9C103 with no other changes. (DI #2262).

Single wire connects microcontrollersAbel Raynus, Armitron International, Melrose, MA
Low-cost µCs, such as Motorola's 68HC705 Series, offer great simplicity at the expense of some useful functions—notably, serial data transmission. Unlike their predecessors, these µCs do not have serial communication interfaces (SCIs), serial peripheral interfaces (SPIs), or simple serial I/O ports (SIOPs). This method describes how you can overcome this deficiency by creating an asynchronous serial interface through µC software. The most obvious way to effect the interface is to use pulse-width coding to differentiate the start pulse and the logic 1 and 0 pulses. You can use any value of pulse-width ratio, depending on your design objectives. This application uses the 1-to-2-to-3 ratio, slightly modified for easy programming. So, logic 0, start, and logic 1 have widths of 0.75, 1.25, and 1.75 msec, respectively (Figure 1).

This example uses 68HC705J1A µCs. The information to transmit accumulates in the output data register of the transmitting µC (Figure 2). The data-transmission subroutine (Listing 1 shows a fragment) generates the start pulse, which is followed by an 8-bit data word that reflects the state of the output data register. This pulse sequence goes, LSB-first, to the data-in input of the receiving µC. In the µC transmitter, you can use any output pin as data out. In the µC receiver, you can use any one of the four lower PortA pins (PA0 through PA3) as data in.

You should program the input pins as positive-edge, external-interrupt inputs. Because pins PA0 to PA3 combine in a logic-OR operation in the µC, you should connect the unused pins to ground to avoid false interruption. You should disable the IRQ pin by connecting it to 5V. The external-interrupt subroutine (Listing 2) restores the data word, which can generate the proper response according to your design objectives. Listing 3 shows a fragment of the receiver routine. The program's watchdog utility lights a red LED to indicate that the communication link between the µCs is broken or that it received the wrong sequence. The method also applies to wireless applications with minor modifications. You can download the complete listings in ZIP format by clicking here.(DI #2265)

Photo-flash charger minimizes parts countSteven Chenetz, Micrel Semiconductor, San Jose, CA
Photo-flash and strobe devices operate by discharging a high-voltage capacitor into a bulb. Charging the capacitor from a battery or other low-voltage source requires a step-up dc/dc converter to boost the voltage, typically to 300V. One way to generate the high voltage is to use a flyback converter. The circuit in Figure 1 provides a simple and reliable way to charge a high-voltage capacitor. The flyback converter performs two functions: It boosts the low-voltage input and provides isolation between the input (battery) and output (high voltage). Its main components are the power transformer; the output diode; the output capacitor; and the MIC3172 controller chip, which combines the switching transistor, voltage regulator, and control logic.

The transformer stores energy when the internal transistor of the MIC3172 turns on, allowing current to flow through the transformer's primary. When the transistor turns off, the stored energy flows through the output rectifying diode and into the capacitor. The voltage across the capacitor increases with each switching cycle until it reaches the preset voltage. The resistive divider R2/R2/R3 and the 1.24V reference in the IC determine the preset output voltage: VOUT= VREF(R1+R2+R3)/R3.

Once the capacitor voltage reaches the preset value, the MIC3172 stops switching. Current flow in the output components cause the capacitor to discharge. The MIC3172 provides occasional energy pulses that keep the capacitor fully charged. When the capacitor discharges into the bulb, the charging process repeats. D1 and D2 clamp any voltage spikes on the collector of the MIC3172 switch node, caused by leakage inductance on the transformer. When the IC's internal transistor turns off, the voltage across the transformer's primary approximately equals the output voltage divided by the turns ratio. The voltage at the transistor collector node (Pin 7) equals the reflected voltage plus the input voltage, plus the voltage spike caused by the leakage energy in the transformer: VSW=(VOUT/N)+VIN+VLEAKAGE.

The collector-node voltage must always be less than 65V. The zener-diode voltage is set greater than the maximum reflected voltage at the transformer primary. For Figure 1, the reflected voltage is 10V. The zener diode is a 12V device, approximately 20% greater than the reflected voltage. The maximum reverse voltage across D2 equals the maximum input voltage. This diode must be an ultrafast or Schottky device, to prevent excessive losses in the diode.

The energy stored in the capacitor is 0.5CV2. The output power that the flyback converter requires to charge the capacitor in a period T is (0.5CV2)/T. The following formula gives the approximate charging time for the converter circuit:

22dieq1.gif (331 bytes)

where IPEAK is the peak current level of the MIC3172 control chip (typically, 1.8A); D is the maximum duty cycle (approximately 0.6); and h is the efficiency of the flyback converter (0.5).

Charging a 300-µF capacitor to 300V from a 5V input requires (300 µFX300V2)/(2X5VX0.6X0.5)=5 sec. For the circuit in Figure 1, the output voltage is potentially lethal. At 300V, the energy in the output capacitor is 27J, more than enough to ruin an otherwise good day. When you lay out the circuit, be sure to provide adequate spacing between the high- and low-voltage sections. The power transformer, such as the Coiltronics CTX04-13770, must have the proper spacing and insulation between the high-voltage secondary and low-voltage primary.

The circuit uses two resistors, R1 and R2, in the upper section of the output to reduce voltage stress, because most commonly available resistors are rated at 200 to 300V—too close to the limit for reliable, long-term operation. If R1 or R2 should open or if R3 shorts, the converter runs open-loop at its maximum duty cycle. This failure mode boosts the voltage far above the preset limit and causes the output capacitor to vent. The circuit in Figure 2 provides overvoltage protection. Be sure that the resistor divider for the overvoltage circuit is separate from the voltage-regulation divider. Set the overvoltage level 15% higher than the output-voltage setting, and make sure it does not exceed the capacitor's voltage rating. (DI #2266).

Generate an analog signal with a µCThomas Schmidt, Microchip Technology, Chandler, AZ
Applications requiring D/A conversion abound, including dual-tone generation, motor-speed control, and offset-voltage generation for a sensor or for battery charging. Most designers believe the D/A converter must be either an integrated module in a µC or an external component; however, a simpler approach is possible. You can generate an analog signal by using a low-cost µC, thereby eliminating the need for external components and thus reducing board space and overall system cost. The RC network in Figure 1 provides an easy way to convert a digital signal into an analog voltage. The RC network, a lowpass filter, connects to an I/O pin of the µC.

To generate an analog signal, the µC charges the capacitor via the resistor. The µC uses PWM to charge the capacitor. The voltage across the capacitor is the analog voltage. When the PWM signal is high, the capacitor charges. When the PWM signal is low, the capacitor discharges. By varying the duty cycle, you can generate a sine wave or any other analog signal. The µC in Figure 1 is a low-cost, 8-bit RISC controller. The PWM signal, generated in software, drives the RC lowpass filter connected to one of the µC's I/O lines.

Listing 1 gives the software code. The PWM routine requires only three general-purpose registers. One register contains the value of the period; the other contains the duty cycle. The program starts by initializing the PWM output pin and the period and duty-cycle registers. The initial duty cycle is 50%. It's assumed in the initialization routine that the RC network connects to pin RA1 of the µC. After initialization, the main subroutine calls the routine in which the PWM signal is generated. In this example, the main routine calls only the PWM_Signal routine. You could easily implement other functions—a keypad or a seven-segment display, for example—just by adding call instructions for subroutines.

The PWM implementation requires a software counter. The register counter stores the software counter. The counter increments each time the program calls the PWM_Signal routine. Each time the counter increments, the program checks to see if the register's value is greater than or equal to the duty cycle. If this condition is true, the program sets the value at the port pin to logic 0. This action signifies that the time for the duty cycle has elapsed. After this time elapses, the routine checks to see if the time for the period is over. If the value of the counter is less than the value of the duty cycle, the PWM signal remains high.

If the value of the counter is greater than the value of the duty cycle, the program compares the counter with the value of the period register. If the value of the counter equals the value of the period register, the period for the PWM signal is over, and the next period starts. The performance of this PWM implementation depends on the number of times the program calls the PWM function from the main routine—the more calls, the higher the resolution. To generate a sine wave, for example, you can store the values for the duty cycle in a look-up table. The values in the look-up table depend on the values and tolerances of the resistor and capacitor and on the desired resolution of the sine wave. (DI #2268).


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