05.21.98 Design Idea

-May 21, 1998

Design Ideas from the May 21, 1998 issue of EDN

Convert binary data to BCD in just 92 µsec
Keith Rubow, Olec Inc, Irvine, CA

The subroutine "FASTBCD" (Listing 1) for 8051 µPs quickly converts 16-bit binary to 24-bit BCD data. The conversion algorithm involves left-shifting bits from the high-order bit of the binary number into the carry bit while left-shifting the carry bits into the low-order bit of a BCD shift register using BCD left-shift operations.

Several optimization tricks account for the speed of this implementation. Inline code eliminates all loop overhead. By placing the binary number in internal bit-addressable memory, bit-move instructions, which require no accumulator, can replace binary-shift operations. However, most of the speed gain results from careful implementation of the BCD left-shift operations. You can easily accomplish a BCD left shift with carry using the 8051's ADDC and then DA instructions. Rather than always performing a 3-byte BCD shift, which is necessary if you implement the program with a loop, each shift need include only as many bytes as are necessary to hold the result after that shift. Single-byte BCD shifts suffice for the first 6 binary bits. For the next 7 bits, you can use 2-byte BCD shifts. Only the last 3 bits require 3-byte BCD shifts.

Further optimization is also possible. You can use a binary left shift in place of a BCD left shift whenever the result cannot produce a half-carry, that is, if the result of the shift cannot exceed 0x09. Combined with careful use of the XCH instruction to minimize cycles used moving data around, these optimizations result in an execution time of just 92 instruction cycles, or 92 µsec with a 12-MHz clock. This conversion time is constant for any input data. The code size is only 91 instructions, totaling 126 bytes. (DI #2202)

High-frequency AGC has digital control
Ron Mancini, Harris Semiconductor, Melbourne, FL

Many systems, especially communications, require AGC that functions at 50 MHz. Self-calibrating systems, such as automatic test equipment, need this high-frequency response but also require digital control of the AGC output voltage. During the calibration cycle, the test equipment calculates the AGC output voltage necessary to achieve the accuracy requirements and then increments the AGC output voltage until the system is within specifications. The AGC circuit in Figure 1 uses a DAC to accomplish the digital control, and because the DAC is the reference input of the AGC circuit, the DAC ultimately sets the AGC output voltage. The HI5731 is a good choice for the DAC, IC3, because it is inexpensive, has an update rate as high as 100 MHz, and functions with 5V supplies. Also, its output interfaces well with the AGC circuit.

The heart of the AGC circuit is a variable-gain amplifier comprising a three-transistor, long-tailed pair configuration: Q1, Q2, and Q3. When the base voltage of Q3 varies, the emitter current of the long-tailed pair changes, which forces a gain change, according to:

where K is a function of the emitter current and VB3 is the base voltage of Q3. The gain-control and bias-stability parameters of the circuit depend on the transistor matching, so the circuit uses a matched, long-tailed array (HFA3102) for Q1 through Q3. The usable range of VB3 is -0.04 to -4.1V, which corresponds to a gain range of 0.8 to 17.6 dB, respectively (VIN=100 mV). This gain span is 16.8 dB. The gain is proportional to R1. Increasing R1 increases the gain, but the gain span stays constant at approximately 16.8 dB, whereas the frequency response decreases.

The gain span limits the AGC circuit's ability to  compensate for input-voltage changes greater than the gain span of 16.8 dB. If the input-voltage change exceeds the gain span, you can double the span by putting two long-tailed pairs in series, which is convenient because the HFA3102 contains two long-tailed pairs. You simply differentially ac-connect the collectors of the first stage to the bases of the second stage. Connecting the bases of the current-source transistors in parallel enables the AGC circuit to maintain the same control function while multiplying the gains of the two long-tailed pairs and thus essentially doubling the gain span.

The long-tailed pair amplifies the input signal to produce the output signal, which in turn is half-wave-rectified by IC1 to produce a quasi-dc control voltage. IC1 is a high-speed op amp with a disconnected lower half of the output stage. Because the output can't go below ground, this IC makes a fine half-wave rectifier or sync stripper. Resistors R2 through R5 set the gain to 2 and add a few millivolts of bias to ensure that the output is always positive. This dc voltage sums with the DAC output in the input stage of IC2's integrator. Because the integrator has a large dc gain, its output voltage swings to any point within the supplies in an attempt to lock the loop. The DAC output sinks current from ground. R6 and R7 form a voltage divider with dc offset. Integrator IC2 compares this dc voltage, which is the reference input, VR, for the AGC circuit, with the output of IC1.

The signal path has excellent frequency response because the HFA3102 is the only component in the signal path. The control path through IC1 has a slightly worse frequency response; to provide control higher than 50 MHz, you must increase R1 or the input signal. The DAC transfers the digital input to an internal register on the rising edge of the clock pulses. The circuit uses the noninverting DAC output to yield a positive-increasing transfer function, but you can obtain the inverse-transfer function by using the inverting DAC output (Table 1).

Fast DAC updates do not affect the output signal with the selected value of C1=1 µF because the integrator filters the change. When the DAC updates, the output voltage slowly changes to the new value. If you use the circuit only for system calibration for which slow DAC updates are the rule, you can use a slower DAC. However, you may have to redesign the integrator circuit--IC2 and associated components--if the DAC's output current swing changes. If you decrease the value of C1, the amplitude of the output signal tends to follow the DAC updates. Thus, if the DAC updates happen in a sinusoidal manner, the DAC's update frequency amplitude-modulates the output signal. (DI #2204)

Comparator adds current limit to V2 controller
Dimitry Goder, Switch Power Inc, Campbell, CA

Many step-down controllers satisfy the need for generating low voltages for µPs and logic. The lower the output voltage, the greater the importance of building a system with fast transient response. Some new controllers use the V2 control architecture, which provides several speed improvements over conventional control schemes by improving the transient response of buck regulators. The problem is that V2 controllers implement short-circuit protection without a current limit.

Although this short-circuit protection is often sufficient, some applications require a true current limit, such as the implementation in Figure 1's circuit. A low-value resistor, R1, performs current sensing. The circuit applies the voltage across this resistor, through R2 and R3, to the inputs of the comparator IC2A. R4 and R8 create initial offset voltages to set the current-limit trip point. When the output current creates a voltage drop across R1 equal to this offset, the comparator's output switches low and shorts IC1's fast-feedback pin, VFFB, to ground, which imitates a short-circuit condition. IC1 then enters "hiccup" mode, turns both Q1 and Q2 off for a time preset by C1, after  which IC1 tries to restart to check whether the fault condition still exists.

The following formula provides an estimate of the current-limit trip point, where 5V is the reference voltage supplied by IC1:

This equation contains neither an input nor an output voltage. You can vary the input supply or the output voltage by selecting different values for feedback components R6 and R7 and still maintain the same current-limit trip point.

To create the correct offset voltage, R5 connects to ground, but R4 needs to connect to a voltage reference, which the circuit obtains in a unique way. IC1's VID0 through VID4 input pins have internal 50-kilohms pullup resistors to IC1's bias voltage of 5V. Because this application requires open VID lines, connecting them does not affect operation and provides access to the 5V reference through an equivalent 10-kilohms resistor. Other parts of the system that provide high-impedance inputs can also use this reference.

The accuracy of this current limit depends on the 5V reference accuracy and the tolerances of R1 through R5, which can be 1% if necessary. Because a standard inexpensive comparator detects the overcurrent condition, this comparator's fairly high input offset directly affects accuracy. This offset sets a practical limit on the minimum drop across the current-sense resistor, R1, at the current-limit inception point defined by the equation for ILIMIT. (DI #2205)

Fleapower oscillator consumes only 1 µA
Yongping Xia, Teldata Inc, Los Angeles, CA

A simple way to make an oscillator is to use a resistor, a capacitor, and a Schmitt trigger (Figure 1a). However, this circuit uses several tens of microamperes because of the voltage transitions at the Schmitt trigger's input. The CMOS device consumes almost no power when the input is either high or low. Whenever the input voltage is at an intermediate level, however, both the p-channel and n-channel transistors turn on partially, producing a significant increase in power consumption. The circuit in Figure 1b uses a Panasonic MN13812C comparator to form an oscillator.

The comparator's threshold is rated at 2 to 2.2V, with approximately 0.1V of hysteresis. It has an inverted output; thus the output is low if VDD is higher than the threshold level, and vice-versa. The measured current consumption in the IC is less than 0.3 µA. The power supply charges C1 through R1. Once the voltage on C1 reaches a certain level, it forces the comparator's output to go low. Then C1 discharges through D1 and R2, until its voltage is low enough to switch the comparator's output from low to high. The voltage change on C1 is the hysteresis of the comparator. With the component values shown in Figure 1b, the oscillation frequency is approximately 50 Hz. Note that the frequency is dependent on the input voltage. It covers the span 44 to 142 Hz as the voltage varies from 3 to 6V. (DI #2206)

Soldering technique reduces pc-board damage
Virgil Lawrence, Micro Linear Corp, San Jose, CA

In testing and troubleshooting surface-mounted components, changing parts can be time consuming. Moreover, desoldering and soldering cycles can loosen and damage circuit-board pads. To minimize damage to the pc board and to quickly remove a component, you can use low-temperature solder. One low-temperature alloy is indium-tin, in a 50/50 mixture. In-Sn melts between 118 and 125°C (tin-lead melts at 183°C). If a component needs replacement, hold the board upside down and heat the area with a heat gun--the component will fall off. If you perform the operation quickly, you'll minimize damage to the board and component.

Proper surface preparation is necessary for the In-Sn alloy to "wet" the surface of the copper. The copper must be clean and you must add flux to allow the alloy to flow freely. You can use rosin dissolved in alcohol. The procedure: Cut a small piece of solder and flow it onto one of the pads. Place the surface-mount component on the pad and melt the soldered pad to its pin while aligning the part. This operation places all the pins flat onto their pads. Then cut small pieces of the alloy solder and flow each piece onto each of the other legs of the component. Indium-tin solder is available from ACI Alloys, 1985 Las Plumas Ave, San Jose, CA 95133, 1-408-259-7337; and Indium Corp of America, 1676 Lincoln Ave, PO Box 269, Utica, NY 13503, 1-800-4INDIUM. (DI #2207)

CMOS gate implements reverse phase control
JC Johnson, Lithonia Lighting, Decatur, GA

The circuit in Figure 1 implements a "reverse" phase control, using only a single CMOS 4001 quad NOR gate. The circuit is known as a reverse phase control because, unlike with common triac or SCR controls, conduction begins at the zero crossing of the ac sine wave. Timing of the turn-off point of the two power MOSFETs then controls the power to the load. This type of phase control is beneficial for use with many different types of loads, as well as incandescent lamps. In addition to reaping the benefits of zero-crossing turn-on, you can make the turn-off rate relatively slow to achieve quiet operation in terms of both EMI and acoustical or filament noise.

A full-wave bridge comprising D1, D2, and the body diodes of the source-to-source-connected FETs provides the power supply for the 4001. Zero-crossing information routes to the input of the first NOR gate through resistors R3 and R4. This inverted signal causes the output to go high for a period of time determined by the R5, R6, and C2 combination. Varying R6, therefore, controls the on-time of the FETs and the resultant power to the load.

Because the CMOS IC has limited drive capability, the turn-off rate is relatively slow. This slow speed provides quiet operation. If you need an even slow turn-off rate, you can insert additional gate resistance. However, note that this modification will increase switching losses, and additional FET losses will ensue. You must provide adequate heat sinking and use conservative ratings for the FETs. The resulting circuit is simple and compact and, in contrast to SCR or triac circuits, does not require special inductances to control rise times.
(DI #(2208)

Optical tachometer provides bidirectional info
Stephen Woodward, University of North Carolina, Chapel Hill

Optical tachometers have many advantages in precision servo applications. Compared with dc-generator types, optical tachs are relatively inexpensive and, because they lack wear-prone commutator brushes, they're long-lived. Frequency-to-voltage conversion circuits provide a convenient means to integrate the output of optical tachs into analog, unidirectional motion-control loops. However, for bidirectional servos, where you need a bipolar angular-velocity readout, you need a more unconventional solution, such as the circuit in Figure 1.

Standard bidirectional optical tachs (such as the one combined with a dc servo motor in the Pittman-Airpax Model 121-5633 motor-tachometer assembly) produce so-called quadrature output signals, as shown in Figures 2a and 2b. During clockwise (CW) rotation (Figure 2a), the positive transitions of output A occur during the positive half-cycles of output B. Counterclockwise (CCW) rotation (Figure 2b) reverses this relationship. The arrangement of CMOS switches SA and SB in Figure 1, each 1/3 of a CD4053B, takes advantage of the quadrature relationship as follows:

As signal A causes SA to flip-flop, C3 repeatedly charges to the 1.2V from VREF, then discharges. Each charge/discharge cycle therefore transfers 1.2x0.0047 µF = 5.6 nCb of charge into the R1-C1 node. The trick that allows bidirectional operation is the charge steering SB provides. During CCW rotation the A/B phase relationship directs SB to connect C3 to the C1 node with timing such that the positive charge pulses that result from each C3 charge to 1.2V deposit onto C1, while the negative discharge pulses dump to ground. As a result, 5.6 nA/Hz = 9.3 nA/RPM (scaled by the 100-pulse/rotation calibration of the Pittman-Airpax tachometer) flows into the R1-C1 node.

Suitable adjustment of R1 can then set a VROT scale factor (allowing for the inversion of the lo  wpass filter) of -1 mV/CCW_RPM. CW rotation reverses the A/B relative phasing such that negative charge pulses corresponding to the discharge of C3 arrive on C1, resulting in VROT = +1 mV/CW_RPM. The component values in Figure 1, in combination with the tachometer parameters, produce a ±2V VROT over the rated speed range of ±2000 RPM. The 12-dB/octave, two-pole lowpass filter provides effective ripple rejection (&1% rms for speeds above 100 RPM) without imposing an excessively slow response time.

Other combinations of tachometer calibration and shaft speed range require other choices for the charge-pump and filter time constants. I suggest the following design limits: C3 & 1/(30,000xfMAX) and R1C1 > 1/fMIN, where fMAX is the full-speed tach-output pulse frequency and fMIN is the minimum-speed tach-output frequency. (DI #2209)

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