06.05.98 Design Idea
June 4, 1998
25-kV generator tests insulationLukasz S'liwczyn'ski and Przemyslaw Krehlik,
University of Mining and Metallurgy, Kraków, Poland
To generate high voltages with proper insulation between the "hot node" and the rest of the circuitry, a car ignition coil can function in place of a high-voltage transformer. These coils have voltage ratings of approximately 20 kV, so you can use them to produce voltages around this value. Because you know the turns ratio of the coil, you can make a stable high-voltage source using a well-controlled voltage at the primary side (Figure 1).
A high-voltage source is a useful device for many applications, including when it is necessary to evaluate the continuity of the dielectric coating deposited on a metal surface. If you also want to estimate the breakdown strength of the coating, this voltage source must be stable. You can easily generate the high voltage with the use of a step-up transformer, but the serious problem of proper insulation emerges. For voltages greater than a few kilovolts, specially constructed transformers with the old insulation are often useful, but these devices are rather expensive and bulky.
The main part of the generator in Figure 1 consists of a free-running converter comprising Q1, Q6, and the transformer, T1. During the first part of the conversion cycle, Q1 is saturated, and energy stores in the magnetic field of T1. D1 is reverse-biased during this time. In the second part of the cycle, Q1 is in cutoff, and the current from the secondary winding of T1 forces D1 into conduction. During this time, energy pumps into C1 through part of the ignition coil, T2. This process allows the voltage, VC1, on C1 to build gradually in a quantized manner. The value of the individual "quantum," Greek Delta, upper caseVC1, is not constant and depends on the initial voltage, VCO, which comes from the previous cycle, as follows:
is the energy stored in the magnetic field of T1 in the first cycle and ICMAX(Q1) is the collector current of Q1 at the end of the first cycle. For the component values in Figure 1, Greek Delta, upper caseEC~0.5 mJ, and ICMAX(Q1)~1A.
R1, R2, and R3 divide down VC1. When this reduced voltage reaches 2.5V, the TL431's 2.5V reference starts to sink the current through R4, so the voltage at the trigger input of the one-shot, IC2, rapidly decreases. An output pulse from IC2 stops the converter for about 8 msec; the emitter node of Q6 goes high, driving it into cutoff. The rising edge of IC2's output pulse also triggers thyristor TH1. The thyristor connects C1, which is charged to the appropriate voltage, directly to the primary winding of the ignition coil, and the high-voltage pulse appears at the "hot" end of the coil. A damped oscillation also starts because the ignition coil and C1 form a resonant circuit.
When a path between the "hot" end and ground exists, part of the energy from the capacitor disperses in the electric arc, and the rest returns to the capacitor through D2. When there is no path from this end of the current to flow, almost all of the energy pumps back into C1. This scheme provides the circuit with relatively high efficiency.
You can calculate the voltage at the "hot" side using the following formula:
where NSEC(T2)/NPRI(T2) is the turns ratio of the ignition coil, which equals 93 in this case. Changing the value of R3 conveniently regulates VHIGH. The accuracy of this voltage is in the range of one "quantum" Greek Delta, upper caseVC1 multiplied by T2's turns ratio. Thus, Greek Delta, upper caseVC1 should be small to achieve good stabilization. On the other hand, a smaller value increases the time between subsequent high-voltage pulses. In this case, the accuracy estimate of the high-voltage pulse is better than 0.5% at 25 kV.
The free-running frequency of the converter depends on the time it takes to lead Q1 out of saturation (first part of the cycle) and the time when the current from the secondary winding of T1 drops to a value near zero (second part of the cycle). This circuit doesn't tightly control this frequency, which isn't a critical design parameter; the values in Figure 1 set the frequency to approximately 6 kHz.
Q2, D3, and D4 prevent VC1 from exceeding about 400V, which protects the generator from producing excessively high voltages. Q3, Q4, Q5, and associated circuitry allow for blocking the converter when the power supply to the circuit is too low. A too-low power-supply level may lead to an output-pulse amplitude from IC2 that is too low to trigger the thyristor, so VC1 may reach a very high value, limited only by the breakdown voltage of the thyristor. This breakdown voltage is the second level of protection, but you can never take too much care in circuits like these.
Two LEDs indicate the status of the power supply: D5 indicates that the level is OK, and D6, that the power supply is too low. One-shot IC3, Q4, and associated components form the source of an alarm, indicated by a flashing D7, when the isolation breaks down or a discontinuity occurs. A simple pushbutton switch turns on the generator.
For the component values in Figure 1, the circuit generates 25-kV pulses with a repetition rate of approximately 0.2 sec. This repetition rate depends on the occurrence or lack of occurrence of the electric arc. Because the amount of energy stored in C1 is relatively low, the energy of the high-voltage pulse is also low, which is good for safety purposes. Note that it is very important and absolutely necessary to connect the part you're testing to the PGND point, because the risk of electric shock exists. (DI #2199)
Scheme speeds access to µP's real-time clockJerzy Chrzaszcz, Warsaw University of Technology, Warsaw, Poland
The DS5000T (Dallas Semiconductors, www.dalsemi.com) is an 8051-compatible processor that integrates nonvolatile memory and a real-time clock. This module has an impressive set of functional extensions and security features, which makes it particularly useful for all-in-one embedded systems.
Unfortunately, access to the real-time clock is complicated and thus inefficient. You access the on-chip real-time-clock registers serially in secondary address space by selecting the ECE2 bit in the MCON register. Instead of just moving the data, you must execute MOVX instructions with appropriate address patterns. First, a 64-bit key is necessary to open the clock, followed by a read or write of the next 64 bits of date/time data. The access routines available from the manufacturer (example file DEMODS5T.SRC) are painfully slow: a byte read takes 106 processor cycles, a byte write takes 112 cycles, and clock opening takes 1929 cycles. Therefore, access to all real-time-clock registers (open/read or open/write sequences) lasts more than 2800 cycles.
Listing 1 uses a different control scheme; the protocol logic resets only during system start-up, which consumes 436 cycles. Also, the listing linearizes the short loops used in the original procedures to open the clock and read/write the data byte. The result is that a byte read takes 51 cycles, a byte write takes 57 cycles, a whole real-time-clock read takes 926 cycles, and a real-time-clock write takes 972 cycles. The potential drawback of this option, with respect to the original approach, is that interrupt-service routines executed during real-time-clock access must not address external data memory, because any MOVX would interfere with the clock-access protocol.
You can download Listing 1 by clicking here: download DI-SIG, #2187 (DI #2187)
Limiting amplifier is digitally programmableV Manoharan, Naval Physical and Oceanographic Laboratory, Kochi, India
Amplitude limiters are necessary in many systems, such as radar and FM receivers, for which the system cannot allow the amplitude of the signal to exceed the given positive, negative, or both limits. In the circuit in Figure 1, amplifier IC4B's maximum output is digitally programmable over ±2 to ±10V in 2n steps, where n is the number of bits of the DAC. IC1, a precision 10V reference, provides a full-scale reference current, IREF=VREF/R1=2 mA, to IC2, a multiplying DAC.
IC3's output voltage, VL, is the sum of the product of the digital word and unipolar reference voltage and IC1's dc offset as follows:
where N can assume values of 0 to 2n-1.
When all digital inputs are set to a logic low, N=0,
For the values of R3, R4, and VREF in this example, VL(MIN)=1V. When all the digital inputs are set to logic high (n=8, and N=255),
For the values of R1 and R2, VL(MAX)~9V.
Within the limiting levels, the amplifier does not modify its input signal but provides a gain of AV=-R6/R5. As VOUT rises above VL+1V--adding 1V overcomes the potential drops of the base-emitter junctions of Q1 and D1--the base-emitter junction of Q1 becomes forward-biased, allowing the collector current to flow to the summing node, thus limiting VOUT. A similar action occurs with Q2 and D2 as VOUT goes below -VL-1V.
You can thus program the limiting levels or the maximum output voltage of the amplifier symmetrically over VL(MIN)+1V to VL(MAX)+1V with a resolution of [(VL(MAX)+1)-(VL(MIN)+1V)]/2nV in accordance with the 8-bit digital-input binary word. The circuit becomes a programmable positive/negative limiting amplifier if you remove the appropriate diode-transistor pairs from the feedback. (DI #2201)
Get more than three colors from a dot-matrix LEDW Kurdthongmee, Nakorn Si Thammarat, Thailand
Dot-matrix LEDs find wide use in advertising displays. Products now on the market range from an inexpensive 5x8 (row-by-column) single-color LED to an expensive 8x8 RGB device. The method provided here allows you to obtain more than three main colors from an 8x8 tricolor LED. In fact, tricolor dot-matrix LEDs have only two LED dies--red and green. When you apply current to one, you obtain a red or a green color. When you apply current to both, orange results. The circuit in Figure 1, used in conjunction with the MCS-51 code in Listing 1, works efficiently in controlling the LED to generate various shades of the three colors.
To add tones or shades of the main colors to the tricolor LED, you do not need to modify the circuit in Figure 1; you need only consider the software. Software modifications consist of adding more color planes or pages of display buffer, adding memory locations (mapped onto the LED dots), and increasing the number of refresh times, in which the controller updates all LED dots to cover all added color planes. For example, if you decide to use four color planes, divided into two red and two green planes, for dot i of the dot-matrix LED, you'll obtain the shades listed in Table 1.
In addition, by allocating eight color planes (four red and four green), you can obtain the color shades listed in Table 2. Note that only the number of ones in the color planes controls color appearance. Therefore, the permutations do not change the color, as long as the numbers of ones in Table 2 remain constant. For example, the values 0110, 1001, 1100, and 0011 for R1 through R4 all produce the same color: orange 50%. You can download Listing 1--as well as the MCS-51 code that produces 13 colors from an 8x8 tricolor LED--from EDN's "Software Center". To download Listing 1, click here: download DI-SIG #2195.
Note that, in practice, bytewide output ports control the LED. To assign a color to a dot, the routine must extract a bit from a byte and then assign the bit value of the selected color plane by plane. (DI #2195)
Implement a nine-data-bit UART on a PCAubrey Kagan, Weidmuller Ltd, Markham, ON, Canada
Many µCs, such as the 8051 and the 68HC11, can support a ninth data bit on the asynchronous serial port. This bit is useful in multidrop applications in which you can use it to denote an address on the serial bus, as opposed to data destined for a particular address. The UART used in IBM PCs (and clones) does not directly support this operating mode. However, through some software manipulation, you can add the PC to a serial bus and integrate it into a ninth-bit system, albeit with some limitations.
The method differs for data reception and transmission. As a result, the PC can work only in half-duplex mode. Because half-duplex communication is common practice on PC networks, this limitation is not a significant drawback. The technique also requires that the CPU check each incoming byte for the ninth bit. (You can usually configure a µC to generate an interrupt when the ninth bit is set.) For the PC to receive the nine bits, it is necessary to treat the ninth bit as a parity bit. Although it's impossible to read the parity bit in the PC's UART directly, it is possible to analyze the received data byte and determine what the parity should be.
If analysis reveals a parity error, then the value of the ninth bit is opposite to the calculated parity. If no error exists, then the value of the ninth bit is equal to the calculated parity. In the 16550 UART, the FIFO includes the three error bits with each data byte, so the parity error (or lack thereof) is always associated with the current data byte. It is possible, however, to disable the FIFO feature. The technique for transmission is slightly different. The 8250/16450/16550 UART has a forced-parity format (also known as a "stick" parity), in which you can set the parity to a one or to a zero. You do this by setting bit 5 (stick parity) and bit 3 (parity enable) in the UART's line-control register (LCR). The transmitted parity bit is then the logical inverse of bit 4 of the LCR.
In the sample code in Listing 1, address 0xff (with bit 9 set) is reserved and used to indicate the last byte of the transmission. The first byte of the transmission is an address, and it transmits with bit 9 set. The RS-232C port connects to an RS-232C/RS-485 converter, where the RTS line controls the direction. The code given here is not interrupt-driven, but you could implement it as an interrupt-driven routine. The code comprises three modules: background (back.cpp), serial procedures (serial.cpp), and memory declaration (mem.cpp). Note that mem.cpp declares one include file (mem.h) for the public memory. You can download the files by clicking here: download DI-SIG #2198. (DI #2198)
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