11.19.98 Design Idea
Power op amps have a real need for active output-current limiting. Most power-amplifier designs rely on the voltage drop across a user-supplied sense resistor to turn on an internal transistor. This method has several drawbacks, notably, an inability to change the current-limit point under program control. The current-limit circuit in Figure 1 allows you to establish the setpoint by applying a voltage to one of the amplifier's pins. With this design, it is possible to set the current-limit point with the output of a DAC, possibly under the control of an embedded µC.
The OPA547 is a true op amp; thus, it does not need a connection to power ground. The current-limit-setting voltage for this IC uses the negative supply as a reference. For single-supply applications in which the negative supply is ground, this referencing technique presents no problem, but for circuits that use a negative supply below ground potential, you need a different technique. The circuit in Figure 1 shifts the reference potential for the control signal from ground to the negative supply. For simplicity, Figure 1 shows the OPA547 as an inverting amplifier, but you can use any op-amp application circuit. The circuit uses an OPA340 for reference shifting because it is capable of rail-to-rail operation on both input and output.
To understand the operation of the reference-shifting circuit, first recognize that the R3-to-R4 voltage divider sets the voltage at IC2's Pin 3. Thus, the intermediate voltage (Vi), as measured from the negative supply, is given by
To find the voltage at IC2's pin 2, note that the current through R3 equals the sum of the currents in R1 and R5, leading to the following expression:
As long as op amp IC2 operates in the linear region, the voltage at Pin 2 equals the voltage at Pin 3, so the value of Vi in each of the expressions is equal. When you substitute the first term into the second, set R1 equal to R2, and combine terms, the resulting expression is
In Figure 1, V1 connects to ground, and you obtain unity gain by setting the coefficient of VC in Equation 3 to 1. If you expand and combine terms, the expression becomes
To change the scalar relationship between the controlling voltage applied to the power op amp, simply set the coefficient term to the desired value and solve Equation 3. To determine the resistor values, consider the worst-case common-mode voltage that IC2 can encounter. OPA547 allows a maximum supply differential of 60V. In an extreme case, the positive supply of the OPA547 connects to ground and the current-limit set voltage is +5V. Equation 1 becomes
which reduces to R3=12R4. Applying this ratio to Equation 4 and setting R3 equal to R1 produces R1=11R5. Selecting from a list of standard 1% resistor values yields the values in Figure 1. Note that the stage operates with a common-mode voltage that equals the negative supply. Errors in the resistor values can produce a significant offset shift. With this circuit, it is possible to set the current limit of the power op amp to a known, repeatable value under program control. (DI #2270).
Accelerometer output gives temperature infoHarvey Weinberg, Analog Devices Inc, Cambridge, MA
The ADXL202 dual-axis micromachined accelerometer from Analog Devices (Norwood, MA) is appropriate for high-resolution applications. In these applications, you sometimes need to know the ambient temperature for control purposes or for circuit-drift compensation. The scheme in Figure 1 offers a novel way to convey temperature information to the system µC without the need for an A/D converter or any additional I/O pins. The ADXL202 delivers two PWM signals that are proportional to the acceleration in its X and Y axes. Current in the RSET resistor sets the period of the PWM signals.
You can use a thermistor in series with or instead of the RSET resistor to vary the PWM period with temperature. However, because of the grossly nonlinear response of thermistors, the PWM period is also grossly nonlinear with temperature. In addition, the thermistor's poor sensitivity at high temperatures may be unacceptable. Although RSET normally connects to ground, you can connect it to any noise-free voltage source ranging from 0 to approximately 1.2V (at which voltage the internal current source runs out of compliance). By connecting RSET to the VOUT pin of a TMP36 temperature sensor, the PWM-period set current varies fairly linearly (within ±5°C) with temperature from -20 to +40°C. Therefore, the PWM period varies linearly with temperature. You can easily extract temperature information from the PWM signal, because you normally measure the period to determine duty cycle. (DI #2271).
Voltage comparator forms pulse demodulatorAbel Raynus, Armatron International, Melrose, MA
To process low-level ultrasound or radio-range pulses, you need a signal-conditioning amplifier followed by a pulse demodulator to translate the signals to dc pulses. Traditionally, you would use a diode-demodulator configuration (for example, the circuit in Figure 1a) with one stage of a single-supply op amp. The circuit in Figure 1b does the same job but uses a voltage comparator instead of a diode demodulator. The key to the method is choosing a threshold voltage (VTH) on the negative comparator input that is slightly higher than the dc level of the amplifier output, which is equal to or close to VCC/2. The R4-to-R6 resistive divider determines the difference between the op-amp bias and the threshold voltage. This difference, calculated to yield an acceptable signal-to-noise voltage, is VCCR5/(R4+R5+R6).
Or, assuming R4=R5+R6, the difference is VCCR5/2R4. R3 and C2 make up a lowpass filter. This pulse demodulator has some advantages: First, its sensitivity is higher than that of a diode demodulator. A 25-mV, 40-kHz, 1-msec input pulse produces a 0.1V output pulse in Figure 1a's circuit, and a 2V output pulse in Figure 1b's circuit. Second, it's convenient and economical to use one more stage of the dual or quad op amp instead of adding discrete components. (DI #2273).
Watchdog-reset catcher aids embedded-system debuggingScott Newell, PCSI, Fort Smith, AR
A simple "junk-box" circuit uses a 4013 CMOS flip-flop and a handful of passive components to determine whether random resets are the result of a blown stack or the result of the watchdog-reset circuit tripping (Figure 1). You can also use this circuit to "grab" and hold other logic level edges like memory or I/O accesses.
A logic-level rising edge at the clock input (Pin 3) of the 4013 clocks the flip-flop. Because the circuit holds the data input (Pin 5) high, the Q output (Pin 1) goes high, which turns on the LED. Once the LED is on, the circuit ignores any further changes at the input.
R1 and C1 are the power-up reset for the flip-flop. At power-up, C1 discharges, which holds the reset input (Pin 4) of the 4013 high, clears the Q output of the 4013, and turns off the LED. C1 charges up to the supply voltage through R1, taking the R input (Pin 4) low to deassert the 4013 reset time. D1 discharges C1 quickly on power-down. S1 is an optional reset switch. C2 is a power-supply bypass capacitor. Don't forget to ground all unused inputs on the 4013. To reset the circuit, either momentarily close S1 or temporarily disconnect power.
You can solder all the parts onto a BNC, which makes it easy to connect a scope probe directly to the watchdog-reset catcher. You can use a clip lead for the power line and easily steal power from the device under test. You can then connect the output of the embedded system's watchdog-reset circuit through the scope probe to the clock input of the 4013.
None of the part values are critical, and many types of flip-flops can substitute for the 4013. A faster flip-flop may be necessary to watch fast signals. Adding an inverter to the input would allow you to catch falling edges, such as active-low reset signals. (DI #2293)
Easily display bit-map images on small-graphic LCDsTodd Fitzsimmons, Densitron Corp, Santa Fe Springs, CA
Combining a high-level language, such as Microsoft Windows, with low-level assembly code or C++ code allows you to display perfect bit-map pictures on your small-graphic LCD screen. You can use Microsoft Paint or any other bit-map-generating program to define and edit the picture. Unlike segmented and alphanumeric LCDs, small-graphic LCDs are fully graphical and can display logos, graphs, or any other image in addition to numbers and characters. The main hurdle to upgrading to this type of display is the software necessary to display the bit-map pictures.
To create your bit maps, you can use any available bit-map program, such as Microsoft Paint. After opening this program, select the Attribute menu. At the prompt, you enter the LCD size you are using and then choose the monochrome-bit-map option. You can now close the Attribute window and start drawing, typing, or pasting the images you want. After saving the pictures, you need to attach the bit maps to the end of your assembled or compiled program in order of their intended use. You can attach them using the COPY/B command in DOS, which differs from the regular COPY command by copying directly as a binary format without adding a byte of data at the end.
To use these attached bit maps, you need a subroutine in your program, such as the 8051 assembly code in Listing 1, which can pull the data out of the lower memory and send it to the display. This code clocks in bit maps to the SED1330 controller chip on a 240X320-pixel display. If your display doesn't use the SED1330 chip, you can still use this code with modifications to the WRCMD and WRDATA subroutines and possibly some alterations on the direction you clock in the data. The direction in the SED1330 is the same as the T6963 controller chip. However, if you use the HD61830, you need to switch the direction of the data; D7 becomes D0, D6 becomes D1, and so on.
For a bit-map program, the first 62 bytes of data call out the protocol for the rest of the bit-map code, such as the type, size and layout of the bit map. Because you have selected the monochrome option and specified layout dimensions using a bit-map-generating program, the subroutine can skip the first 62 bytes. The 63rd byte defines the first 8 pixels in the lower left corner of the display. The following bytes go sequentially to the screen until you hit the right edge of your display. The next byte is either the first byte on the next row up on the left side or a padded zero that the bit-map program places there to maintain certain integers for row length.
Padded zeros are necessary when the number of bytes in a row are not divisible by four. If you have 16 bytes of data per row, no padded zeros are necessary. However, if there are 30 bytes per row, two padded zeros are necessary to bring the number of bytes to 32. Your internal program must disregard these zeros before going on with the 33rd byte of data (Table 1).
Consider the example of driving a 128X240-pixel display. You would set up your assembly code to strip off and discard the first 62 bytes of data from the bit-map file. The 63rd byte is then the first byte in the lower left of the LCD. Then, the next 29 bytes of data (240/8=30) appear directly in the display. The code must then discard the next 2 bytes of padded zeros. The next byte of data then appear in the next row up and over on the left. A user continues this process until all 128 lines are completed.
If you access the upper bit-map memory by using the data pointer address in your µP, then, when you paint the first page and increment the data pointer, you see the first byte of the next picture in your list.
An important difference between a bit map and an LCD is that, in bit-map programs, a binary 1 is an off pixel, and a binary 0 is an on pixel. So, a user must perform an exclusive-OR with FFh to properly view the bytes. Without this operation, your picture would be the inverse image of your original picture. (DI #2295)
CMOS inverter VCO tunes octave to UHFShawn Stafford, AM Communications Inc, Quakertown, PA
A robust and versatile vco provides a stable output to 300 MHz (Figure 1). The circuit's simplicity, unconditional stability, and consistent high-drive capability over an octave make the oscillator ideal for many applications, such as synthesized sources, local oscillators, and transmitters. The AHC logic family (Texas Instruments, www.ti.com) makes the circuit's performance possible. AHC is a relatively new line of CMOS logic whose high speeds and good noise performance allow oscillator operation into regions in which bipolar-junction-transistor and FET designs prevail.
The oscillator topology is a modified Colpitts oscillator for which two hyperabrupt varactor diodes create the capacitive divider. The SMV-1255-004 (Alpha Industries, www.alphaind.com) encloses two varactors in one SOT-23 package (Figure 1a). The capacitance-voltage ratio of these varactors allows linear tuning over an octave with less than 4V (Figure 1b). You can substitute other varactors as long as the loaded Q of the resonant circuit is high enough to ensure start-up oscillation, but tuning characteristics may change. The inductor is a wound spring type chosen to maximize resonant Q. Oscillation is unstable when you use a low-Q, surface-mount-wound, chip-type inductor. The 100-kOhm resistor biases the gate to provide the gain and the 180° of phase shift necessary for oscillation. A lowpass filter with a low-frequency cutoff is highly recommended on the IC's power pin. Without this filter, incidental modulation from power-supply noise and pickup easily contaminate the oscillator signal. A dedicated voltage regulator is also recommended in noisy environments, but the filter is still necessary to keep the signal as clean as possible.
With a 5V supply, current consumption is approximately 25 mA±1 or 2 mA, depending on the frequency of oscillation. Using a 33 Ohm series resistor can reduce the current to 8 mA and supply enough power for reliable oscillation. The cascaded gates provide extra buffering and drive; the output resistor improves match with additional buffering. If your design needs a known constant output impedance, you can substitute a resistive match pad for the output resistor and maintain a considerable output level. Figure 1c shows the drive capability over frequency at mid-VHF, as well as level variation of less than 0.5 dB over the selected octave. Temperature effects on level are minimal with less than 1-dB change over 0 to 75°C, and worst-case harmonics are always better than -12 dBc. (DI #2294)
Pushbutton or logic controls nonvolatile DACStephen Woodward, University of North Carolina, Chapel Hill, NC
For manual control of analog signals, it's hard to beat the venerable precision multiturn potentiometer's simplicity, resolution, and power-off nonvolatility. When digital control of an analog parameter is the design objective, a universe of DACs is available to the designer. The circuit in Figure 1, however, has manual-pushbutton and CMOS/TTL-compatible digital interfaces to a 10-bit, nonvolatile, two- or four-quadrant multiplying DAC. The heart of the circuit is the Xicor (Milpitas, CA) X9511 PushPot series of digitally controlled potentiometers. These devices implement a convenient up/down response to either ground-referenced contact closures (with built-in debounce and pullup provisions) or open-collector/drain digital pulses.
Other useful features of these digital potentiometers include a ±5V analog-signal range and automatic storage and retrieval of settings with power-on/off cycles via an on-chip EEPROM. The potentiometer's only shortcoming in this context that its resolution is inadequate for precision applications (only 32 distinct settings, equivalent to a mere five bits). To overcome this limitation, the circuit combines two PushPots with a summing op-amp buffer to achieve nearly 10-bit resolution. IC1 provides a weighted sum of the wiper voltages of P2 (coarse input) and P1 (fine input) in the ratio of 25.5-to-1. This operation provides a composite resolution of 32·(25.5+1)=848 distinct settings, equivalent to 9.7 bits.
The missing 0.3 bits are lost to the good-but-still-only-finite differential linearity of the X9511 (Xicor specifies ±0.2 LSBs) and the consequent need to give a less-than-ideal weight (32X0.8 instead of 32) to P2 to guarantee overall DAC monotonicity. The resultant two-quadrant (R2=10 kV, R3 omitted) gain equation is VOUT/VIN=(25.5XP2+P1-31)/761. Thus, two-quadrant gain runs from -0.04 to 1.04 in steps of 0.0013, as P1 and P2 settings vary from (0,0) to (31,31).
Optionally, you can obtain four-quadrant multiplication by adding one resistor to the circuit, with the value R3=R2=20 kV. Gain then becomes VOUT/VIN= (25.5XP2+P1-410)/380 and ranges from -1.08 to 1.08 in steps of 0.0026, as P1 and P2 vary from 0 to 31. The loading of P1 by R1 is light enough to produce a negligible effect on linearity. Connecting Pin 7 (automatic store enable) of P1 and Pin 7 of P2 to ground enables automatic storage of potentiometer settings to internal EEPROM upon power-down. The circuit then automatically retrieves the settings on power-up. (DI #2269).
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