06.18.98 Design Idea
June 18, 1998
Demodulator makes low-cost optical trackerSteven Sarns, Kesta Technology Inc, Wheat Ridge, CO
A project required building a synchronous-demodulator circuit to track a line drawn on paper. The beauty of the synchronous-modulator/demodulator approach is its inherent noise rejection. The method rejects nearly all out-of-band noise, whether from internal drift or external illumination. This rejection is a boon in optical tracking, where the return signal is inevitably buried in 120-Hz ambient light, amplifier offsets, and temperature drifts. The circuit in Figure 1 is inexpensive, and it operates from 5V dc. The circuit scans eight LED/sensor pairs every 22 msec and stores the result in eight sample/hold (S/H) capacitors for interrogation by a µP-driven ADC. The purpose of the circuit is to determine which sensor is above the line.
The 74HC4060 generates a chopper signal at a rate of 3 kHz. Every eight chopper cycles, the circuit increments the three address lines, thereby selecting the LED to illuminate through the 74HC138 multiplexer. The chopper signal gates the 138 on and off, thus producing the synchronous modulation of the signal at the selected LED. A 74HC051 demultiplexes the received signal from the sensor array, using the three address lines. A 2.5V rail is the signal reference for the next two stages of amplification to produce maximum signal swing. The signal ac-couples to a gain stage, set nominally at a gain of 20. Two poles of lowpass filtering provide first-order 120-Hz rejection.
The next amplifier switches between gains of 1 and -1. This switching is the heart of the synchronous demodulator. If no noise were present with the incoming signal, the output would appear as a dc level equal to one-half the incoming peak-to-peak signal. The circuit asynchronously amplifies any noise appearing on the incoming signal, such that the output of the demodulator swings above and below the expected dc level by the amount of the noise. The next stage of amplification averages out this noise signal. The third stage of amplification averages the demodulator's output and references the result to ground, such that an increasing return signal produces an increasing output.
A gain of four allows the output signal to approach 4V, while still providing the demodulator stage enough overhead to reject noise. The signal multiplexes onto eight S/H capacitors, using another 74HC4051 and the three address lines. Resistor R1 prevents third-stage oscillation by isolating the amplifier from the S/H capacitors. The circuit limits the actual sample period to the last four chopper cycles to allow the demodulator to settle after changing channels. A portion of the signal, lowpass-filtered and buffered, drives the 10-to-1 current mirror (Q1, Q2) to establish the drive current to the LEDs. This arrangement results in a constant average output signal of 2.5V over a range of distances from 0.05 to 0.5 in.
The signal from the sensors undergoes a delay because of the relatively slow photodetectors. Therefore, the chopper signal must also have a delay (via R2C1) before controlling the ±1 gain switch, so the phase matches as closely as possible. Select the appropriate delay to minimize the carrier-frequency noise on the output signal. You can use low-cost components throughout. Suitable choices include an LM358AN for IC3 and a CA3260 for IC5. You should use CMOS op amps because of the high resistance values in the circuit. The second stage should have rail-to-rail output capability to reject noise effectively. Amplifier saturation appears on the output as noise.
Amplifier speed is not of great concern, because the phototransistors are the slowest components in the processing path. Individual sensors vary from unit to unit. You can select the eight emitter resistors to produce matching outputs, if desired. You can place the eight LEDs along the edge of the pc board on the solder side, and the eight sensors on the component side, spaced 0.2 in. apart. Using visible-light LEDs, a line drawn by a "Sharpie" marker approximately 30 mils wide results in a 50% reduction of the signal of the channel directly over the line at a 1-in. distance. A number-2 pencil line results in a 5% signal reduction at a 0.25-in. distance. The higher output of infrared LEDs would further improve the performance. Listing 1 gives the Basic source code for the tracker operation. To download the routine, go into the Software Center to download the files from DI-SIG, #2211. (DI #2211)
µC implements pushbutton light dimmerWilliam Grill, Riverhead Systems, Littleton, CO
Using a 12C508 Microchip µC, as described in the EDN, Dec 18, 1997, Design Idea, "Controller provides multimode phase control," you can implement an inexpensive dimmer control to provide constant-power control of a line-powered load (Figure 1). The previously described controller evaluated an input frequency relative to its local time reference and scaled a tabled phase offset to define the specific phase-step timing relative to the zero crossings of the monitored input. A two-button, debounced counter provided manual indexing of the tabled offset table. The table used 5º steps. Redefinition of the table allowed nonlinear phase indexing to accommodate specific requirements, including constant power or luminescence profiles. The code, usable from 1 Hz to 1 kHz, accommodated common 60-Hz line-power applications, such as the one described here.
You can connect the 12C508 controller in Figure 1 directly to the ac line by limiting the line pin's input current to a few microamperes. The combination of the 3.2-Mohm resistor and the use of the µC's internal diode in pin 2 allows monitoring the ac line with only a small phase error. A simple power converter and an inexpensive LM78L05 linear regulator provide the VDD supply to the µC directly from the ac power line. With the controller-mode and sense pins 3 and 4 grounded, the processed output pulse couples directly to the triac, Q1, using an optically coupled MOC3010 diac. In Figure 2a, the typical output waveform references to MT2 of the triac. This application modifies the phase table to provide a 78-step index, calculated to provide constant power. Thus, the areas under the curve are approximately the same for all steps (Figure 2b). To download the µC code for this application, go into the Software Center to download the files from DI-SIG, #2212. (DI #2212)
Charger selects between full and trickle chargeAjmal Godil, Linear Technology Corp, Milpitas, CA
The circuit in Figure 1 charges a lead-acid battery at full charge voltage while monitoring the charge current. When the charge current decays to approximately 0.1C, where C is the capacity of the battery, the charger automatically switches to a lower trickle-charge voltage. The battery can remain in this state for a long time, minimizing any degradation of battery life.
The most common method for charging sealed lead-acid batteries is constant-voltage charging, which means that the charger voltage is uniform, regardless of the state of the battery. When the battery is fully discharged, its voltage is less than the charge voltage and the current flow into the battery is large. As the battery charges, its voltage increases, and the charge current decreases. Although the current of a constant-voltage charger starts out high, it decays exponentially. Because of this exponential decay, you can potentially overcharge the battery using a fast-charging scheme. However, the charger in Figure 1 avoids overcharging by always monitoring the charge current.
The 75W sealed lead-acid battery charger for seven tall D cells in Figure 1 uses a high-power, current-mode switching regulator (IC2). The required full-charge voltage is 2.45V/cell, and the trickle-charge voltage is 2.35V/cell. Discharged batteries can draw as much as 16A of charge current because they have low internal resistance. The charger circuit is current-limited at 4A. This current limit is equivalent to 1C, which is the maximum current into the battery and the charger's safe limit.
When you plug a discharged battery into the charger, the battery attempts to draw as much as 16A. Because the charger is current-limited, it delivers only about 4A, and the battery voltage starts rising. When the charge current drops below 4A, IC2's internal feedback loop takes over and regulates to a charging voltage of 17.15V. As the battery charges, it draws less and less charge current (Figure 2). When the charge current decays to 0.5A (0.125C), it produces a voltage drop of 6.25 mV across R1. IC1A amplifies this voltage by 100, which trips comparator IC1B and turns off Q2. This action lowers the feedback resistance and sets the lower trickle-charge voltage to 16.45V. The charge current continues to fall as the battery charges. Additionally, the circuit automatically adjusts the charge voltage as a function of temperature by using R2, a silicon temperature sensor, to give a -3 mV/ºC temperature coefficient. (DI #2203)
Power supply runs off battery or wall adapterDavid Bell, Linear Technology Corp, Milpitas, CA
Most portable products need to operate from both a battery and an external wall adapter. Although conceptually simple, implementing a robust and bulletproof design that properly switches between these two power sources can be challenging. The circuit in Figure 1a delivers 5V at 50 mA from four AAA alkaline cells or from a 6V wall adapter, which is enough power for many handheld applications. This circuit meets the following design criteria:
The heart of the circuit is IC1, a charge-pump dc/dc converter. This converter is capable of step-up or down operation over a 3.2 to 10V input range. The IC uses no inductors and requires only one external charge-pump capacitor for dc/dc conversion. Pulling SHDN low disables the 5V output, or you can connect SHDN directly to VIN, pin 7, if shutdown is unnecessary.
Dual p-channel MOSFETs, Q1 and Q2, operate as input power switches to IC1. The back-to-back MOSFET connection allows these power switches to block current in both directions, preventing conduction through the body diode. Depending on the operating mode, either Q1 or Q2 turns on to supply power to IC1. Figure 1b shows the switch-over between the wall adapter and battery. The upper trace is the 6V wall-adapter voltage turning on and off; the middle trace is the input to IC1, showing the voltage change between a 3.2V battery and a 6V wall adapter. The bottom trace is the output of the dc/dc converter delivering a constant 5V throughout the process.
Dual diode D1 provides voltage to the MOSFET gates via R3, R4, and R5. A comparator within IC1 monitors the voltage on the LBI pin and releases the LBO output when the voltage on LBI goes above 1.145V. The R1/R2 voltage divider determines the external-power-good threshold, which is around 4.5V in this case. When the wall adapter is absent, the LBO pin is low. This low level forces the gates of Q2 low, which puts Q2 in a conducting mode, and keeps Q4 off. With Q4 off, R3 and R4 pull the gates of Q1 high, which keeps Q1 turned off. When the wall-adapter input voltage goes above 4.5V, LBO goes high, reversing the states of Q1 and Q2. The circuit includes Q3 and Q5 to hold the gates of Q2 low when a wall adapter is absent. Without these transistors, Q2 would never turn on when the user first installs batteries in the product, and IC1 would forever be stranded without power.
Zener diode D2 and R3 prevent the design from exceeding Q1's 8V VGS(MAX) rating with a high wall-adapter voltage of as much as 10V. Figure 1a indicates 5% values for R1 and R2; 5% is sufficient accuracy for setting the relatively noncritical threshold for switch-over from batteries to a wall adapter. All other resistors are assumed 1 or 2% accurate.
The entire circuit consumes very little pc-board area. IC1 is a standard SO-8 footprint, and Q1 and Q2 are in the even smaller "micro" SO-8 package. All the remaining transistors and diodes are in SOT-23 packages.
The circuit has the same efficiency as a linear regulator in step-down mode, yet it does something no linear regulator can do, which is boost the battery voltage. When the input voltage drops below approximately 5.2V, IC1 switches to charge-pump doubler operation. This switch-over initially results in a big efficiency drop in IC1--from approximately 90% to just less than 50%, according to the data sheet--but efficiency again improves as the input voltage drops. At an input voltage of 3.2V, IC1's efficiency is approximately 80%. (DI #2220)
Four ICs implement video AGC and dc restoreTamara Ahrens and Mike Wong, Elantec Semiconductor Inc, Milpitas, CA
Four ICs--a multiplier, a sync separator, an op amp, and a dc-restore IC--along with a handful of passive components can implement a complete AGC and dc-restore circuit for video signals (Figure 1). The circuit consists of three main paths: the signal path, the gain-control path, and the dc-restore path. The input video signal first passes through an attenuator so that the circuit can handle oversized voltages. The attenuated signal drives IC1, which multiplies this signal by the gain-control voltage. Both the gain-control and the dc-restore path use the output of the multiplier.
IC2's sync separator recovers the timing-logic outputs of the video signal and also provides a level-out signal. This signal corresponds to twice the tip-to-porch voltage that the gain servo op-amp, IC4, compares with a reference voltage of 0.7V, which is nominal for the NTSC standard. The integrated output of IC4 drives the second input of multiplier IC1. You can adjust the potentiometer for proper peak-to-peak amplitude through this servo system. In the event of a loss of signal, which pin 10 of the sync separator indicates, an npn transistor turns on, shunting the op amp's input to ground and sending the VGAIN control signal to its maximum setting.
IC2 also provides the dc-restore signal. The burst-detect output informs IC3's dc-restore IC when to hold the previous value and when to restore the current output voltages. When the burst-detect signal is logic 1, the circuit stores the offset voltage on coupling capacitor C1. Conversely, when a logic 0 appears at pin 4 of IC3, the dc offset is null. You can reduce the value of C1 to allow for compensation of larger correction voltages at the cost of greater droop during the hold time. IC3 also contains an amplifier capable of driving back-terminated 75ohm cable.
Two passive components associated with IC2 are critical. The resistance on pin 2 determines the minimum signal level that the circuit can detect. A value of 82 kohm allows IC2 to detect signals greater than 100 mV at the sync tip. The other critical value is RESET at pin 12. This resistor sets the reference current and, subsequently, all the internal timing functions, for the entire chip. For NTSC video with a 15.7-kHz scan rate, a value of 681 kohm with 1% tolerance is necessary. (DI #2221)
"Useless" masked µCs make useful PC peripheralsAlec Bath, Motorola Inc, Northbrook, IL
A software bug or a new code revision can often render hundreds of masked µCs all but useless for production purposes. However, by tapping into the 68HC11's bootstrap mode, you can attach these µCs to a PC's RS-232C serial port and put them to work. In the MC68HC11E9, 512 bytes of RAM are available for downloading a user's program. 512 bytes of EEPROM are also available to the programmer, as well as an 8-bit ADC, two serial ports, various timer functions, and many I/O ports. The masked-ROM locations are unused.
Figure 1 shows the connection from a 68HC11E9 (IC1) to a PC's eight-pin RS-232C serial port. The HC11 resets into bootstrap mode, and a QuickBasic program downloads an S-record file at 1200 baud. Upon receipt of the final byte, the program executes at the start of RAM. IC2 is a 5V-only RS-232C level converter. For proper communication synchronization, an 8-MHz crystal is necessary, although other crystal/baud-rate combinations are possible.
The QuickBasic program "bootload.bas" loads an assembled S-record file and strips the header, footer, and checksum information. The program then converts the ASCII text into raw hexadecimal data, adds a preamble $FF character for communications synchronization, and transmits the data at 1200 baud out COM port 1. The HC11's internal boot-loader-ROM program configures its SCI asynchronous serial port, looks for an $FF character, and downloads a program in RAM, starting at $0000. To download the bootload.bas program, go into the Software Center to download the file from DI-SIG, #2222. (DI #2222)
Use a printer port to record digital waveformsDean Shen, Dycam Inc, Chatsworth, CA
To record or capture special waveforms, those that appear once or have no fixed frequency, the usual technique is to use a logic analyzer or a storage oscilloscope. However, these tools are very expensive. Moreover, because of limited memory, a storage scope can record fewer than 1000 samples. The technique presented here provides an alternative method to recording digital waveforms. The idea is to use the PC's printer port to sample waveforms, and the PC's memory to store data. The large memory capacity of PCs allows you to store large samples. For example, 60 kbytes of memory can store 8360,000=480,000 samples.
To sample data as fast as possible and to equalize sample periods, you use Debug directly to write an assembly program to implement the sampling procedure. Once the PC's memory stores the data, it is easy to display the waveform or to save it in a file. You use QBasic to display the waveform. To compare the recorded waveform and the waveform from a standard signal generator, you calculate the sample period. We have used the method successfully to record many different digital waveforms. Figure 1 shows the sampling circuit. Listing 2 gives the Debug sampling program. After execution, the routine saves the segment of recorded data in 40h:FEh.
The Basic program in Listing 1 can easily access the data. This method uses a Dallas Semiconductor one-wire communications protocol. The PC is a 33-MHz 80486 machine; the sample period is approximately 2.03 µsec. The method shown here can record only one channel signal. However, you can easily modify the circuit and the sampling program to record two- and four-channel signals. To download the executable Debug routine and the QBasic source code, go into the Software Center to download the files from DI-SIG, #2210. (DI #2210)
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