03.02.98 Design Idea
|March 2, 1998
Synchronizing controller detects baud rateWilliam Grill, Riverhead Systems, Littleton, CO
A simple and inexpensive implementation using an eight-pin 12C508 controller (Microchip Technology, Chandler, AZ) provides both bit-rate detection and a synchronous, appended-clock output from an asynchronous input-data stream (Figure 1a).
This implementation relies on two code sequences (Figure 1b). A training sequence first identifies the bit rate. This sequence begins with register and counter initialization followed by a gap detection. Following the detected, 0.325-sec, high-true gap, the controller monitors eight transitions. Between each transition, a local loop counter counts the number of loops necessary to arrive at the next transition. The controller tests the accumulated number of loops between transitions to identify the count period that resulted in the fewest loops. After processing all eight transitions of the training sequence, the controller evaluates the shortest maintained count according to a table index based on the training loop's code length. Because the controller's timing is crystal-based and the loop's path lengths are equal, the processed count corresponds to the bit rate that the controller then uses to define a delay necessary for the second code sequence.
The second output-code sequence begins by locating a fixed, second gap of approximately 40 msec. This time allows the controller to completely terminate the training sequence before beginning the controller's main iterative loop. The sequence then takes the delay, identified earlier, and processes the serial input data on Pin 4 to the output at Pin 7 while maintaining complementary clocks on pins 5 and 6. Equalizing the instruction paths for this code sequence is a key requirement of this application.
The controller uses a 3.6864-MHz crystal to provide precise baud-rate timing. This scheme allows the combined code applications to support 300- to 9600-bps asynchronous inputs. An 8-bit training pattern of 55 (hex) allows multiple single-bit isolated transitions to qualify the detected bit rate (Figure 1b).
The output-sequence code provides resynchronization of the clock-related delay counters at the input data-transition edges on Pin 4. This resynchronization allows flexibility in supporting data-bit edge delays and distortion and variations in the controller's crystal or external timing reference's accuracy. You can download applicable code by clicking here: Download. (DI #2158)
Charge Li-ion batteries from ac line voltageMatt Schindler, Maxim Integrated Products, Sunnyvale, CA
Li-ion battery chargers must apply constant current when the battery charge is low and constant voltage when the battery charge is high. To avoid battery damage, the tolerance on the applied voltage must be less than 1%. The charger in Figure 1 complies with these requirements.
The circuit converts energy from 120V ac to a regulated voltage or current as necessary to charge two Li-ion cells in series. IC1, a popular controller for offline power-supply applications, operates as a forward converter, producing an isolated, half-wave-rectified battery voltage or current from the full-wave-rectified line voltage. This converter operates at 250 kHz and handles ac inputs from 90 to 135V.
IC2 is a chemistry-independent battery charger. Though designed to drive an external transistor, in this case, it drives the MOC211 optoisolator to control IC1 across the isolation barrier. IC2's internal circuitry sets the battery voltage to 8.4V±0.5%. The 0.1V current-sense resistor, R1, and ISET resistor, R2, set the battery current to 1A±2%. (DI #2161)
Emissions killers trap common-mode currentsGlen Chenier, Fujitsu Network Communications, Richardson, TX
An unshielded twisted-pair cable that is transformer-coupled to a digital system can easily act as a radiating antenna, not because of the differential analog signal the cable carries, but because of common-mode currents induced by unwanted stray coupling from the digital portions of the system. These currents from fast digital transitions contain harmonics in the hundreds of megahertz and can be a nightmare to design engineers who have to make systems conform to radiated-emissions limits.
If the coupling transformer has a center tap on the winding to which the cable attaches, you can use this tap to reduce the level of these nasty common-mode currents on the cable. Connecting the tap to a quiet earth ground provides a path to shunt these currents harmlessly to earth before they can sneak out the cable and radiate (Figure 1). A capacitor in the connection provides the same RF grounding function but presents a high impedance to any 60-Hz ground loop currents if the far end of the cable also connects to a ground-referenced transformer winding. This capacitor should be only a few hundred picofarads, must have short leads and circuit traces between transformer tap and good earth ground, and must have a sufficiently high voltage rating to withstand high-voltage transients as the end market requires.
The technique works as follows: The opposite ends of the transformer winding are balanced with respect to ground; that is, the windings push and pull with equal amplitude but opposite polarity on each and every transmitted data symbol. The center of the transformer is the "pivot" on which the winding balances. As such, this pivot point is neutral relative to ground; an actual connection to ground makes no difference to the differential information signal.
If a common-mode signal impresses both conductors, the resulting currents at opposite ends of the winding flow both toward and away from the center tap in the same phase. This flow causes magnetic cancellation between the two halves of the winding, and the resulting inductance is very low, resulting only in the residual leakage inductance. In this way, both conductors have a low-impedance path to earth ground without affecting the wanted differential signal. Note that filtering each conductor with an RC network also provides the low-impedance path to ground; unfortunately, this filter also destroys the differential signal in high-bit-rate applications.
The technique in Figure 1 also helps reduce susceptibility to common-mode currents that external fields induce; the unwanted currents pass harmlessly through each half of the transformer winding and cancel each other out. Interwinding capacitance--the usual mechanism by which common-mode voltages can affect transformer-coupled receiver inputs--is less critical because both conductors have a low-impedance path to ground, resulting in minimum common-mode voltage on each conductor.
Using a common-mode choke in addition to the center-tap trap results in a real common-mode killer. The two techniques complement each other, and it can be helpful to use both together in stubborn cases. As Figure 1 indicates, you can place the common-mode choke--virtually a transformer on its side--in line with the cable, preferably at a point just before the cable exits the (ideally) shielded enclosure to avoid stray-noise pickup on the cable after the choke. A similar but opposite magnetic magic takes place in the common-mode choke, which must present a high series impedance instead of a low shunt impedance to common-mode currents. The winding turns ratio is 1-to-1, and the polarity is such that the magnetic fields from the differential signal now cancel, resulting in almost zero attenuation other than that resulting from the leakage inductance. On the other hand, the common-mode currents cause magnetic addition, which results in high impedance and reduces the level of unwanted currents.
You can also make a common-mode choke by slipping a large ferrite sleeve over the two conductors of the twisted pairs or by winding one or more turns of the twisted pairs through a large toroid "doughnut." Many ferrite suppliers make these sleeves and toroids just for this purpose. Also, well-balanced common-mode chokes of the more conventional transformerlike construction are also readily available from datacomm-transformer suppliers.
Two capacitors following the common-mode choke can reduce high-frequency differential-mode emissions caused by non-common-mode currents. (DI #2160)
Isolated driver forms solid-state circuit breakerBob Watson, Corley Manufacturing Co, Chattanooga, TN
The circuit in Figure 1 allows standard TTL logic levels to safely drive a high-power dc load. The circuit provides for both signal and ground isolation as well as a solid-state circuit breaker.
The input signal drives IC1A, which in turn provides drive current for optoisolator IC2A. In the absence of an overcurrent condition, IC2B conducts the signal to the gate of the MOSFET. When sufficient current passes through current-sense resistor, R1, to cause a voltage drop of approximately 0.7V, SCR Q1 latches on. When Q1 is on, the circuit pulls Pin 3 of IC2B low, which stops the transistor side of IC2B from conducting. R2 then holds the gate of the MOSFET low, which prevents it from conducting until you reset the SCR. (DI #2163)
µC measures high-frequency signalsStan D'Souza, Microchip Technology Inc, Chandler, AZ
To measure a high-frequency signal using an 8-bit µC, the time period of the measured frequency must be relatively close to the internal clock of the µC. For example, if the internal clock period is 1 µsec, then the maximum frequency that you can measure is 1 MHz in most µC applications.
However, you can use the circuit in Figure 1a to measure a frequency much higher than the internal clock frequency of the µC. This circuit uses an external binary ripple counter operating in asynchronous mode. The circuit gates the incoming frequency to the counter using NAND gates and control lines from the µC. To enable counting, the µC sets CNTL1 and CNTL2 to 1. Once the measurement time is complete, CNTL1 resets to 0, which stops further inputs to the counter.
To read the value of the low 12 bits of the frequency, the µC toggles CNTL2 N times until the internal 8-bit timer increments by one. The low 12-bit value of the frequency is then equal to 4096-N. Reading the value of the counter in this manner requires only one I/O line as opposed to 12 lines to read the counter's 12 bits. In combination with the internal 8-bit counter in the µC, a 20-bit frequency measurement is possible. The limiting factor of the measurement is the maximum frequency input to the NAND gates and the ripple counter.
Although the circuit in Figure 1a is straightforward, the circuit does involve the additional cost of a 14-pin NAND gate and a 16-pin counter, which may be undesirable in many applications. In PICmicro 8-bit µCs, the internal 8-bit counter/timer, TMR0, has an associated 8-bit divider, or prescaler. The counter has read/write capability, but you can't read the prescaler value. You can modify Figure 1a's circuit using a PICmicro µC to implement a 16-bit frequency counter (Figure 1b).
This circuit uses the internal 8-bit prescaler to divide the incoming frequency. The circuit feeds the output of the prescaler to the 8-bit timer, TMR0, for measurement. As with Figure 1a's circuit, once the gate time is over, CNTL1 blocks additional clocks from the input signal. Then, CNTL2 pulses the 8-bit prescaler N times until the 8-bit timer/counter, TMR0, increments by 1. In this case, the lower 8-bit value of the measured frequency equals 256-N. The µC then concatenates the value of the counter with the 8-bit timer's value to give a 16-bit value of the measured frequency.
Figure 1c shows a further simplification of the circuit in Figure 1b by replacing the NAND gates with two transistors and four resistors. To start the counter, the µC configures CNTL1 and CNTL2 as inputs or in a high-impedance mode. Thus, the circuit directs the incoming signal to the prescaler and in turn to the 8-bit timer/counter, TMR0. When the gate time is complete, the µC makes CNTL1 an output going low. A low CNTL1 deactivates the transistor, whose output becomes an open collector. The µC can now make CNTL2 an output normally high and going low to pulse the input to the prescaler. The µC pulses CNTL2 low N times until the value of TMR0 increments by 1. The low 8-bit value of the frequency is equal to 256-N. To begin counting again, the µC reads the value of TMR0, which clears the prescaler, and again configures CNTL1 and CNTL2 as inputs.
Note that the architecture of the PICmicro µC allows accurate timekeeping for the gating pulse because the timing of a software loop is predictable and accurate to within one instruction cycle; a PICmicro µC executes each instruction in one cycle, except for branch instructions, which take two cycles. (DI #2164)
Microamps monitor dual-supply batteriesBruce Anderson, University of Wisconsin--Madison
The low-power circuit in Figure 1 monitors two 9V batteries in a dual-supply configuration and turns on the Battery Low LED if either battery voltage drops below its limit. It also provides two shutdown signals you can use to turn off voltage regulators, such as Maxim's MAX663/664 positive and negative regulators. By using low-power voltage references and op amps, the circuit holds the current drain to approximately 45 µA from each battery, with the positive drain rising to approximately 1 mA when the LED turns on.
Each battery voltage undergoes comparison with a Motorola LM385Z 1.2V reference, using a Maxim 7612 op amp with hysteresis via a 2-Megaohm resistor (R5 and R11). Cross-coupling via the 3-Megaohm resistors (R6 and R12) ensures that if either shutdown signal goes true, both do, and the circuit locks up in the shutdown state with the Battery Low LED illuminated. C1 and C3 delay the reference voltages so that when the batteries switch on, the circuit comes up in the proper state. Positive Shutdown is at the positive rail when true. Negative Shutdown is at the negative rail when true. The values shown allow you to adjust the battery-low limits over a range of approximately 3.8 to 8.1V. For our applications with Eveready EN22 alkaline batteries, we typically set the limits at 6.5V. This setting uses a good portion of the battery life, yet allows some reserve for continued operation after the LED comes on.
The circuit has two convenient features that were unforeseen before testing. One is that when the batteries switch off, the LED flashes briefly as the decoupling capacitors discharge. The flashing indicates that the batteries are not so totally dead that they cannot light the LED. The other is that the LM385 has an initial turn-on voltage about 10% higher than the steady-state 1.2V reference. Thus, when you switch the batteries on, they must have a voltage about 10% higher than the steady-state threshold to be considered good. So if the Battery Low LED stays off when the device turns on, the batteries will remain good for a while. Of course, if you are not using the shutdown signals to turn off regulators, you can set the threshold so that your device will continue to operate for a period after the LED comes on. Using the battery-discharge characteristics and your circuit's voltage and current requirements, you can select a threshold that gives appropriate reserve for your application. (DI #2169)
Program provides integer-to-binary conversionBert Erickson, Fayetteville, NY
Binary numbers rarely appear in applications of C or C++ programs, so any reference to converting from an integer to a binary number is usually relegated to a few simple examples in the appendix. However, when you're working with codes for communication systems, terms such as parity, checksum, distance, weight, and block codes are much easier to verify with a check solution when they are in binary form. C and C++ statements do use integers for manipulations that have binary implications. However, when the analysis gets down to the binary-number level, the conversion from integers is hard to find in the libraries supplied with the compiler. The cintbin and classicC functions in Listings 1 and 2 convert an integer in the main function to a binary number that remains available in the main function.
The ones and zeros in the elements of the array correspond to the location of bits in the customary binary number. You can compile the C++ cintbin version as listed. Readers who have an ANSI C compiler can use the program preceded by // in Listing 2. For long integers, refer to the revised edition of Microsoft C Programming for the PC by Robert Lafore. The first part of the listing is only a driver that has a call to the function and a printout for the binary number. You can use the bits in the binary number in any additional statements.
The first argument in the call should be 31 or less to provide some leading zeros but large enough to make sure the most significant bit is included. The temporary variable z and the return value provide some assurance that the result is valid. The statements in both functions are self-explanatory, so the only thing left to do is to compile one of the programs and enter 31 4,294,967,295 with a space after 31 to verify the 32-bit binary number 1111 1111 1111 1111 1111 1111 1111 1111. You can download the listings by clicking here: Download. (DI #2156)
| EDN Access | Feedback | Table of Contents |
|Copyright c 1997 EDN Magazine, EDN Access. EDN is a registered trademark of Reed Properties Inc, used under license. EDN is published by Cahners Publishing Company, a unit of Reed Elsevier Inc.|