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08.17.98  Design Idea

-August 17, 1998

 



PLEASE NOTE: FIGURES WILL LINK TO A PDF FILE

August 17, 1998

Don't let slow circuits slow down the system

Kevin Skahill, Cypress Semiconductor, San Jose, CA
A combinatorial function with a propagation delay greater than the system clock period does not necessarily prevent a design from operating at frequency. By taking advantage of arrival times or carefully using wait states, a design can give the combinatorial circuit sufficient time to settle before sampling the output, thereby allowing the remaining logic to operate at frequency.

In other words, you may still be able to implement a design even if the static-timing analysis indicates that a block of logic violates the specified clock period. The key is understanding when inputs arrive, when the design needs stable outputs, and whether you can use registers to time the sampling of those signals.

Consider the implementation of an adder and a state machine in a CPLD. The state machine operates at a system frequency of 66 MHz. The adder requires a propagation delay of 20 nsec. At first glance, you might conclude that the entire design is infeasible because the adder can operate only at 50 MHz. However, if the design doesn't require the output on the next clock cycle after the inputs arrive, then you can design the circuit to allow sufficient time for the adder to settle before sampling the output.

Figure 1 illustrates that a state machine operates from the system clock, as do the input and output registers of the adder. However, the input and output registers to the adder maintain their contents until enabled. The state machine generates the enable signals. When the system latches the inputs, the adder has two clock periods, or 30 nsec, before the output register is enabled. The associated timing diagram for this design is implemented in the 64-macrocell CY7C373i CPLD using Warp2 VHDL synthesis software (Cypress Semiconductor, www.cypress.com) (Figure 2). The output is unavailable until 20 nsec after the rising edge of the first clock, so the design doesn't sample the output until the second rising edge.

In this case, the state machine times the input- and output-enable signals to match the arrival of the data. In general, for a free-running combinatorial circuit, a simple clock divider can control the enable signals. In the case of a divide-by-two clock divider, a T-type flip-flop asserts an enable every other clock cycle. (DI #2237)

Java applet computes standard valuesVance Campbell, Digital Radio Communications Corp, American Fork, UT
The Java applet in Listing 1 implements a standard-resistor value calculator in a form that is suitable for use on a Web page or an internal intranet. Java solves the portability and platform-support problems of previously published Basic programs. See Reference 1 to learn more about the theory behind this computation algorithm.

This applet provides a text field in which the value is input and the standard value is displayed. You can compile the applet using Sun Microsystems' (www.sun.com) Java developers kit, or you can use the applet directly from the author's Web site (www.geocities.com/CapeCanaveral/5716/). Listing 2 contains a sample html file that shows how to load the applet from a Web page. (DI #2238)
Reference
1. Bidwell, David C "Basic calculates standard resistances," EDN, March 3, 1982, pg 167.

Attenuators nullify temperature deviationsSemyon Lapushin, Electronic System Products, A Division of Antec, Norcross, GA
You can use the circuits in Figure 1 to temperature-compensate a dc voltage of any circuit if the voltage-versus-temperature curve meets the following criteria:
  • The curve is stable in time at the same temperature;

  • The curve is reproducible under repeated temperature cycling;

  • The curve is monotonic within the necessary after-compensation accuracy (in other words, the curve doesn't have local fluctuations that exceed the maximum-allowable after-compensation flatness);

  • The curve has either a positive or negative slope or is C-shaped.


The goal is to make the entire profile of the compensated voltage, VC, as close to VC at 25°C as possible. For all three circuits, you can use an NTC thermistor with a value of 1 kOhm±5% at room temperature (RTO=1 kOhm). The temperature profile of the selected thermistor, an NTHS-J14, is in Table 1.

Figure 1a works as a temperature-controlled attenuator to compensate for a voltage profile with a positive slope (Figure 2a). This method compensates for three points on the curve: VO, or the voltage at room temperature; VN, the most negative temperature; and VP, the most positive temperature. The following three equations describe the state of the network:

[equation]

where RTO, RTN, and RTP are the values of RT at the three temperature points, and where VO, VN, and VP are the corresponding values of V. In addition to these six known parameters, the equations include three circuit variables: RS, RP, and R1. Finally, the equations include the compensated voltage, which must be less than the minimum values of VO, VN, and VP: VCO, VN, VP).

A corresponding MathCAD 5.0 program (di2249.zip) finds the variables RS, RP, R1 from the equations as a function of parameter values.These values correspond to temperatures of -40, 25, and 85°C. The compensated curve in Figure 2a shows that the value of VC is 1.8V, which is about half of VO. Note that if the values of network resistors derived from the equations are negative, you must decrease the value of VC.

Figure 2a also shows that the output voltage (VC) remains relatively stable and the input voltage (V) changes with temperature. The final VC is a result of an Excel program calculation based on the equations at every temperature point. The experimentally obtained data varies from the calculated values by amounts that are within the sensitivity of the ±5% tolerance of RT and the ±1% tolerance of RS, RP, and R1. This program also shows that the deviation of the resistors within their worst-case tolerances degrades accuracy by less than 0.2%. For the compensated curve in Figure 2a, the maximum relative deviation from average decreased from 21% (in the uncompensated case) to 1.04%.

Similarly, you can use the network in Figure 1b to compensate a voltage that has a negative temperature slope, and you can use Figure 1c, which employs two thermistors, to compensate C-shaped curves with positive or negative slopes. For the C-shaped case, another MathCAD 5.0 program solves a system of four equations that are similar to Equation 1 and finds the variables RP1, RS1, RP2, RS2 as a function of parameter values. These values correspond to temperatures -40, 10, 35, and 85°C on the uncompensated curve in Figure 2b. The other curve in Figure 2b shows the compensated response. In this case, the uncompensated curve has a relatively small deviation—less than 2.6%—which compensation further reduces to 0.46%.

The accuracy of the compensation of the C-shaped curves is lower than for the curves with positive or negative slopes and more sensitive to the deviation of the original curve. You can fine-tune the accuracy by appropriately selecting the four points (VN1, VN2, VP1, VP2) on the curve and the value of VC. You may also have to change the value of VC if the Mathcad program can't find a solution. Excel programs can assist in evaluating the calculated accuracy. (DI #2249)
Table 1—NTHS-J14 thermistor profile
Temperature (°C)RT (kOhm)
-4014.4
-154.685
101.68
251
350.741
600.35
850.1855

CAD technique helps tweak capacitor valuesHugh Adams, Adams Consulting, Fort Walton Beach, FL
Determining the appropriate size of filter capacitors in power-supply designs is often difficult. Most designers tend to overdo it and add unnecessary cost and size to the design. However, you can use a stepping feature in Microcap V (Spectrum Software, www.spectrumsoft.com) to ascertain the trade-offs and choose the best values for your design.

Figure 1 shows a simple 18V open-loop regulator circuit with an input circuit that you can use to test the regulator for input ripple rejection over a 10 Hz to 10 MHz bandwidth. You can ignore the input circuit because it only simulates a test fixture in the analysis.

The simulations aim to determine the smallest values of C1 and C2 that allow the circuit to achieve reasonable ripple rejection. Figure 2a shows the resultant rejection in the ratio of output ripple to input ripple over the stated frequency range, as C1 steps from 1 to 151 mF in 50-mF steps. Figure 2b shows the result when C2 steps from 1 to 16 mF in 5-mF steps. Changes in C1 don't produce radically different curves; changes in C2 produce more variations in the amount of ripple because of the well-known capacitance-multiplier effect of Q1. The impedance of Q1 represents a large resistance between the source and C1. This resistance allows a much smaller value of C1 to produce the same effect at a given frequency as a larger value.

Figure 2c shows the final result with C1 equal to 1 mF and C2 equal to 5 mF. When used together, these two minimum effective values result in acceptably low levels of ripple using half the capacitance for C2 and 1/100 the capacitance for C1. The advantage of these lower capacitance values outweighs the 14-dB difference in rejection between Figure 2c and the lowest curves in Figure 2b. Other applications may have other rejection requirements, and thus you must choose the capacitor accordingly. This technique makes it easy to determine the trade-offs and make the right choice. (DI #2240)

Crystal oscillator overcomes typical drawbacksRon Mancini and Jeff Lies, Harris Semiconductor, Melbourne, FL
Most crystal oscillators suffer from three drawbacks: They can't drive much of a load, the duty cycle isn't adjustable, and the duty cycle drifts. The crystal oscillator in Figure 1 solves these problems. Three parallel gates drive heavy loads, the duty cycle is adjustable from 25 to 75%; and feedback minimizes the drift.

The oscillator circuit comprises C1, C2, C3, R1, R2, R3, one gate, and the crystal. R1 and R3 bias the gate in its linear region, and the capacitors form a p filter around the crystal. The p network preserves the crystal's Q factor, provides the correct loading capacitance for the crystal, and prevents oscillations at spur frequencies. R2 limits the crystal's power dissipation to 5 mW. The difference between the output voltage (3.9V) and the input voltage (2V) is about 1.9V, which is a typical TTL threshold voltage. Therefore, you can use the following equation to select R2, even though the equation is an optimistic approximation:

[equation]

Thus, for PCRYSTAL=5 mW and R2=722 Ohm, you should select R2=750 Ohm.

R2 and C3 form a lowpass filter whose -3-dB point should be at FOSC/8 or higher. This choice prevents spurious high-frequency oscillations. The -3-dB point for this design equals FOSC/8=625 kHz. You can use the following equation to calculate C3:

[equation]

Because C1 must have a large value to minimize the effects of stray capacitance changes, 510 pF is an acceptable value. The series combination of C1, C2, and C3 must equal the specified load capacitance for a parallel resonant crystal, so that

[equation]

The load capacitance for the selected crystal is 32 pF, which requires a C2 of 38.5 pF or a real value of 39 pF. With the component values in Figure 1, the circuit oscillates at 5 MHz with a parallel resonant crystal. The duty cycle is a function of the gate bias-point resistors. Therefore, variations in logic gates cause variations in duty cycle—typically, 30 to 65% with normal manufacturing tolerances. The duty-cycle adjustment compensates for this variation, and the feedback provided by the op amps reduces drifts to a fraction of 1%.

IC1A integrates the oscillator output into a dc level. The ICL7621A works well for this function because it has a high input impedance and a large output swing and because it operates with a 5V supply. IC2A sums the integrated signal with the duty-cycle setpoint voltage to create an error signal. The feedback loop keeps the duty cycle constant by changing the oscillator gate's bias point until the error signal reaches zero.

The circuit parallels the output gates for increased drive capability. All gates are in the same IC, so you can safely connect them in parallel, and the oscillator/output gate delays match well under reasonable loading conditions. When necessary, the input-enable signal gates the oscillator output with just a gate delay. Turning the oscillator off and on incurs an oscillator start-up delay, which lasts microseconds or longer. You can replace the NAND gates with inverters if the enable function is unnecessary.

If the output loading changes during operation, you can take the feedback point from the output to compensate for varying loads. Beware that ringing resulting from poorly terminated transmission lines can cause duty-cycle variations when the feedback comes directly from the output. If minimizing duty-cycle drift is unimportant, feedback is unnecessary, so you can split R3 into a 2.5-kOhm fixed resistor and a 5-kOhm variable resistor that connects to ground. This selection of R3 enables a 25 to 75% duty-cycle adjustment. For different logic families, you must verify, and possible reselect, the gate-bias resistors. ( DI #2254)

Replace an external gate with a resistorStan D'Souza, Microchip Technology Inc, Chandler, AZ
You can significantly reduce costs in a single-chip µC application by replacing an external gate with a resistor. In applications that require the gating of an external signal for measurement purposes, the traditional circuit uses an external two-input AND gate (Figure 1a). An I/O line from the µC normally controls one input to the NAND gate, which in turn enables and disables the incoming signal.

Although this circuit is straightforward, the additional overhead of adding an external gate in a single-chip application makes the circuit undesirable. A more elegant and cost-effective gate replaces the AND gate with a resistor, one end of which ties directly to the input and I/O pin (Figure 1b).

To enable the signal to the µC input, the circuit configures the I/O line as an input. This configuration ensures that, during the measurement operation, the I/O line and resistor play no role in the circuit and that the incoming signal passes directly to the µC for measurement.

Configuring the I/O line as an output that's driven either high or low disables the signal, effectively stopping further input to the µC. At this point, the input signal is basically shut off from affecting the measurement. You can repeat the process when another measurement is necessary.

The value of the series resistor determines how much current the I/O pin can source or sink. Because some µCs have a typical sink/source current value as high as 25 mA, the typical minimum resistor value for a 5V system can be 200 Ohm. In most applications, the source that supplies the input signal typically drives about 50 to 10 mA of current. Thus it's best to choose a µC that has a high sink/source capability on the I/O lines, such as one from the PICmicro 8-bit family. (DI #2236)

 



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