EDN Access — 07.18.96 Delay line implements clock doubler
Design Ideas:July 18, 1996
Delay line implements clock doubler
Timing delays are undesirable in most digital circuits. However, in some cases, delays can be useful—to deal with a µP-speed-compatibility issue, for example. The circuit in Figure 1a uses a silicon T/4 delay line and an XOR gate to implement a simple clock doubler. Using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock.
SAE magnetics (HK) Ltd, Guang Dong Province, China
Using a more precise delay line, the circuit can output a triple clock (Figure 1b). The MSD1000 series of silicon delay lines from Maxim Integrated Products (Sunnyvale, CA) provides 5- to 500-nsec delays with nominal accuracies of ±5%. The manufacturer can also customize standard delays to meet special needs. (DI #1899)EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.