Xilinx fires a 5G solution shot across the bow of RF and data converter companies

-February 21, 2017

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I remember when specialty companies like Graychip made their mark in the '90s with digital down conversion (DDC) and digital up conversion (DUC) ICs along with traditional semiconductor companies that had the high speed op amps and data converters to complete the signal chain in a base station. Digital pre-distortion (DPD) ICs were also used at that time along with the special sauce of an algorithm that improved the distortion of the transmit signal chain. Then, along came the FPGA solutions that upended the traditional market for the DPD and the DUC and DDC solutions. Xilinx had one of those disruptive solutions.

Well, now we are on the road to 5G and fast approaching the need for better signal chain solutions and Xilinx has rocked the industry again. They have embedded RF-class analog technology into their 16nm, all programmable MPSoC architecture. This new RFSoC design does not need discrete external data converters because they have integrated high speed/high performance ADCs and DACs into their SoC solution with a direct RF sampling architecture, bringing the industry closer to the goal of the software defined radio. This added flexibility in the digital domain is great news for 5G with massive MIMO, as well as for millimeter wave wireless backhaul needs. Xilinx claims an amazing board footprint and power savings reduction of 50 to 75%.

Moving from 4G to 5G

Today's 4G radio access networks (RAN) have a bundle of lossy coaxial cables and wires to deal with in order to connect with remote radio heads (RRH). This system has power losses that need to be mitigated (Figure 1).


Figure 1 The remote radio lossy design (Image courtesy of Xilinx)

For many years, designers have been on the ever-elusive quest of moving the digital and analog radios closer and closer to the antenna. The first step toward this goal was using active antenna arrays (Figure 2).

Figure 2 The interim step of the active antenna helped mitigate power losses from the antenna to the radio. (Image courtesy of Xilinx)

 The active antenna array worked for 4G systems, but with the advent of the huge number of connected devices for a viable 5G system, designers needed something new. Along came massive MIMO and beam-forming. These were a good start toward making 5G a reality. The problem that designers needed to solve were the 32, 256 up to 1024 individual antennas needed in a 2D array. This phased-array architecture enables high-resolution beam steering along with lower power consumption. Now high density installations will create much higher density per individual cell (Figure 3).


Figure 3 A massive MIMO 2D array (Image courtesy of Xilinx)

Taking this design to the next level, layouts like mounting “tiles” along the exterior of a building, or billboards/signs, etc. are possible (Figure 4).


Figure 4 New topologies like antennal tiles along the exterior of a building are leading to ultra-densification. (Image courtesy of Xilinx)

 Now here is where the Xilinx all-programmable RFSoC will enable an architecture to leap-frog to the next major step toward realizing 5G—a system design that is scalable for a flexible design with sub-arrays (Figure 5).


Figure 5 The Xilinx sub-arrays will enable scalability in a flexible design architecture to fit the particular location. (Image courtesy of Xilinx)

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