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EDN -- 01.04.96 PLL IC forms simple digital phase shifte

-January 04, 1996

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Design Ideas:January 4, 1996

PLL IC forms simple digital phase shifter


Haldun Karaca,
DE University
Bornova, Izmir, Turkey


A phase shifter is a vital block in some signal-processing and clock-distribution applications. Another important application is in benchmarking digital phase detectors. The circuit in Figure 1, an especially appropriate one for evaluating phase detectors, uses only two industry-standard ICs (CD4046 and LM311). It relies on digital PLL techniques.

Although it’s possible to use one timing capacitor between pins 6 and 7 of the CD4046 PLL IC (as is customary), the circuit in Figure 1 uses two equal-valued capacitors (C1A and C1B), with one end of each grounded. This configuration eliminates nonlinearities that could result with a short-duration negative swing to -0.6V at the start of the ramps. With the 12V supply to the CD4046, the peak value of the ramps on pin 6 or pin 7 is approximately 6V. The 10-kOhm potentiometer and fixed resistor generate a reference voltage of 6V maximum.

The adjustable reference connects to the negative input of the LM311 comparator. The positive input can connect to either pin 6 or pin 7 of the CD4046. When the ramp reaches the reference voltage (see Figure 2a), a leading-edge transition occurs at the output of the comparator, which connects to one of the CD4046’s phase-comparator inputs. The PLL ensures that no phase difference exists between pins 14 and 3 of the CD4046. A reference-controlled phase shift results between pins 14 and 4 of the CD4046.

With this circuit, you can easily obtain between 0 and 180° phase shift, both lagging and leading, and you can easily adjust the amount of the shift with the potentiometer. When pin 6 of the CD4046 connects to the comparator, the VCO output lags (Figure 2a) with respect to the input signal at pin 4 of the CD4046. Again, you can use the potentiometer to control the amount of the lag. Connecting the comparator to pin 7 of the CD4046 causes the VCO output to lead the input (Figure 2b). (DI #1797)


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Copyright c 1996 EDN Magazine. EDN is a registered trademark of Reed Properties Inc, used under license.

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